regarding tetramax tool response

[pavankumarmnnit]

tetramax .lib

read netlist banyan.vhd

BUILD> read netlist banyan.spf

BUILD>
BUILD> run build_model banyan

BUILD> run drc banyan.spf

BUILD> drc

BUILD> drc
i am unable to change to drc mode and i dont know wheter tool is working properly or not................... i am sending snapshot of tool when it is running i opened it by using the path tmaxgui after sourcing .cshrc of synopsys................

expecting reply.,...................................

 

[santhosh007]

tetramax .db

it looks like you are not reading your lib and pin constraints so on.. Here is the typical tmax dofile.. try with these and let me know

read netlist netlists/netlist.v -format verilog
read netlist lib/lib.v

report modules -undefined
run build_model <TOPLEVEL MODULE NAME>
// pin constriants
add pi constraint 1 scanmode
// clocks and reset
add clocks 0 scanclk0 -shift -timing 100 50 80 40
// scan chain details
add scan chain chain0 scanin_0 scanout_0
add scan enables 1 scanen
run drc
run atpg -auto
report scan chains
write...

 

[pavankumarmnnit]

add clocks tetramax

hello freind , i have seen your reply. i have tried commands what u have send but no change
in response............

My problem is that i have an rtl design (behavioural) in "vhdl" of banyan switch. The
architecture needs scan cells to be stiched so that the circuit becomes dft circuit..

So i have done them using dc(dft compiler ) and i have generated STIL PROTOCOL file which is required by tmax . I have done this by using commands provided in dft manual.
I am sending whole work done upto now . I need to get test vectors for inserted scan chain using tmax atpg tool .

By the by regarding library model we are using class.db provided by synopsys in dc ( for student edition ) then in tmax what i should use......

Any way go through whole design and tell me the mistakes ..............

expecting reply,
thanking u.........

 

[santhosh007]

tmax add clocks 0

The first thing is.. for the Tmax pattern generation STIL file is not required.. it will use the generate itself.

Regarding the library , you need to read the verilog std cells which corresponding to the class.db. you can find them in the same path under verilog dir.

you make sure that you need to read the synthesized netlist (output of DC) with the scan chains implemented into tmax not RTL.

please let me know.