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Recent content by Patrick520

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    Can Calibre XRC do substrate noise coupling simulation ?

    Hi, there is only calibre DRC LVS XRC suit in my lab. I design a RFIC layout which will work at beyond 3GHz. I just wanner know can Calibre XRC can simulate the substrate noise coupling effect? And how to do that ? Is there any tutorial ? I use tsmc technology. Thanks.
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    Please expain to me why DLL has no jitter accumulation...

    Re: Please expain to me why DLL has no jitter accumulation.. Hi. Can you tell me what is the name of the Deam's book? Thanks.
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    How can I accelerate the PSS simulation of VCO?

    Hi I am design a vco for zigbee receiver, whose oscillating frequency is 2.4GHz. In Spectre ADE, I choose the PSS (shooting) simulation. But I find that simulation speed is too slow. The simulating netlist presents as: pss: time=13.19us (3.23 m%), step=1.839ps ( 200 p%) pss: time=13.26us (3.25...
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    Where is the "Spectre info' statement"?

    Hi. I am reading a book, Designer's guide to spice and spectre. In the page 36 of that book, there are lines of words like below: " Carefully check all parameter values to assure they(parameter of component) are reasonable. Use the list and delete the nomod options with SPICE to get a complete...
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    How to import CST or HFSS result into Cadence Spectre?

    Hi! I am new to RFIC design. I wanna do a simulation for a whole RF transceiver including the antenna and the wave propagation. If I design an antenna in CST or HFSS. How can I import their result inot Cadence spectre? If without the sepecific character data of antenna, I think I...
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    question on verilogA term "ddt" usage

    Hi! I am new to verilogA. I wanna describes an analog block which has a function of differentiating. So, I describes a sentence as below: "V(out)<+ ddt(V(in))" But however, when using spectre to simulate it. There is error like "V(t0,out)= 6.28 GV exceeds the blowup...
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    [SOLVED] [Help] error on simulation about verilogA block

    Hi. I am new to Cadence IC5141. I am doing a simple simulation. I use Cadence IC5141 on RHEL5.4. I use model writer to write a delay cell, the verilogA code is listed here: " `include "discipline.h" `include "constants.h" module delay_elem (vin, vout); input vin; output vout; electrical...
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    When using verilogA to describe a block, can parameters like NF, IIP3 be described?

    Hi. I am new to verilogA. I am trying to design a IR-UWB trasceiver. And I am now in the stage of doing system simulation. I want to make sure my calculation results of NF, IIP3 of each receiver's block can work correctly. But in Cadence, there seems no blocks which can generate Gaussian...
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    Noise Figure calculation problem

    I am recently reading a book, "CMOS Cellular receiver front-ends from specification to realization " by Johan Janssens。 In the subset 3.5.2, page41, there is a description as below: “The required noise figure of the complete receive path is 8.87 dB, of which 3 dB has already been assigned to...

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