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The 370V is definitely not sagging by more than 1V.
---------- Post added at 17:58 ---------- Previous post was at 17:55 ----------
Well, the gate voltage looks okay, I think (?). The supply definitely does not droop. So, by process of elimination, measurement error?
Thanks to all for the excellent advice. I don't have any fast mechanical relays or CM chokes in the lab right now--I'll order them, but that will take a few days to come in. Otherwise, I don't think I have the ability to troubleshoot this any further, and there's other engineering to be done, so...
I can still see this effect when the full voltage is on screen (At 50V/div) so I don't think it's the scope. This is the only HV probe I have, but I'll try dialing down the 370 to something more reasonable to see if I see similar effects on low voltage probes.
I showed the 10M there, but I...
I'm not sure what is meant by a 370V-X connection. I'm using a battery to generate the 16V below 370V I show. (I'll use a DC-DC flyback converter later)
The pic I posted is the P-Channel MOSFET's gate waveform. Notice this is a P-Channel MOSFET, so a negative going edge is what you'd expect for...
Hi all,
I'm using the MTP2P50EG P-Channel power MOSFET in order to attempt to switch a high voltage. I've prototyped the attached circuit, along with a scope screenshot of what I'm seeing at the output.
The trouble is that the waveform quickly shoots up to 350V in ~200ns, but then takes a long...
Hi all,
I need to build a circuit that has it's normal "ground" terminal ~10V below the high side of the output of a DC-DC converter whose output is 400V above true signal ground. Between the 400V and 390V terminals, the circuit needs to provide a reference voltage that is stiff to load...
Hi all:
I'm working independently through "The Art of Electronics" 2nd Ed. I have a question about Exercise 2.9 (p. 84)
The exercise states:
"Verify that an 8degC rise in ambient temperature will cause a base-voltage-biased grounded emitter stage to saturate, assuming that it was initially...
Hi All,
I'm using a DG535 to pulse an LED with 10ns pulses ~4V tall in order to test a photomultiplier tube. However, the problem is that the reflections re-trigger the LED in an unwanted way. I need to terminate the LED, but I'm not sure how to get the best combination of maximum LED...
Positive it's in the file list.
I failed to mention that files with entity/architecture declarations CAN use the A1 constant from the mydefsA package. The trouble is that files which define another package cannot.
Hi all,
I have a VHDL file (mydefsA.vhd) which contains a package with one definition in it:
------------------------------------------------------------------------------
library IEEE:
library WORK;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package mydefsA is
constant A1 ...
Hi all,
I'm working on VHDL firmware for a project involving a bunch of FPGAs. Most of the FPGAs have similar firmware, with only things like their ID changing from FPGA to FPGA. I want to create a VHDL file with configuration data, where all constants specific to the FPGA are listed, and then...
Fair enough, but what I'm really interested in is understanding whether or not this would work--I want to deepen my understanding of the subject.
Let me try to ask the questions I'm trying to understand a bit more plainly:
1.) If a flip flop's output goes metastable due to a timing violation...
Hi all,
It seems to me that whether or not the flip flop in the following example goes metastable doesn't really matter. I'd like to know if others agree/disagree.
The input to the flip flop it an active low signal asynchronous to the flipflop's clock, which is always asserted for longer than...
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