Is metastability okay in this case?

[pastro]

Hi all,

It seems to me that whether or not the flip flop in the following example goes metastable doesn't really matter. I'd like to know if others agree/disagree.

The input to the flip flop it an active low signal asynchronous to the flipflop's clock, which is always asserted for longer than two clock cycles. The circuitry which uses the output of this flip only looks for a falling edge, and once this edge is detected, doesn't sample the output again for it again for many clock cycles (i.e. the output of the flip flop is used as a "trigger").

If the input to the flip flop violates the flip flop's setup and hold time, then the possibilities seem to me that: 1.) the output is interpreted as a 1, but will be seen as a 0 on the next clock cycle, so we don't care 2.) the output is interpreted as a 0, which is what we want.

So, in this case, it seems to be that there is no need for a synchronizer. Am I right?

 

[TrickyDicky]

Is it really worth the hassle just adding a 2nd flip flop?

 

[FvM]

Metastability means, that the output of the flip-flop will be undefined for a certain amount of time, e.g. after one clock cycle, when it's copied to another flip-flop. The probability can be estimated for a particular logic family. You have to decide, if it's acceptable for your design. Also a single FF is acting as a synchronizer, but more succeptible to metastable events.

 

[pastro]

Is it really worth the hassle just adding a 2nd flip flop?

Fair enough, but what I'm really interested in is understanding whether or not this would work--I want to deepen my understanding of the subject.

Let me try to ask the questions I'm trying to understand a bit more plainly:

1.) If a flip flop's output goes metastable due to a timing violation, is it's output guaranteed to come out of metastability and accurately reflect the the input on the next clock tick, provided the new input to the flip flop doesn't create a new timing violation?

2.) If a second flip flop clocks in the output of the first flip flop (this is a basic two flip flop synchronizer) while flip flop 1's output is metastable, what happens to the output of the second flip flop? Can you be assured the output of the second flip flop will be a solid 0 or 1--but not something in between--after clocking in the metastable signal, or could the output of the second flip flop go into "no man's land"?

 

[mrflibble]

2.) If a second flip flop clocks in the output of the first flip flop (this is a basic two flip flop synchronizer) while flip flop 1's output is metastable, what happens to the output of the second flip flop?

As far as I understand it, when the output of the 1st flip-flop is still in "no man's land" after 1 full clock cycle, then the 2nd flip-flop can go metastable as well. It's a matter of statistics. The longer the settling time the 1st flip-flop has, the lower the chance of the 2nd flip-flop going metastable. If you felt like it, you could add a 3rd flip-flop for even lower chances of the 3rd one going metastable.

I just stick with 2 flip-flop synchronizers, where I try to place them as close together as possible for the largest possible settling time.

I also find it useful to stick with a naming convention like "randomname_meta" and "randomname_sync" for the 1st and 2nd stage flipflops.

 

[std_match]

1.) If a flip flop's output goes metastable due to a timing violation, is it's output guaranteed to come out of metastability and accurately reflect the the input on the next clock tick, provided the new input to the flip flop doesn't create a new timing violation?

2.) If a second flip flop clocks in the output of the first flip flop (this is a basic two flip flop synchronizer) while flip flop 1's output is metastable, what happens to the output of the second flip flop? Can you be assured the output of the second flip flop will be a solid 0 or 1--but not something in between--after clocking in the metastable signal, or could the output of the second flip flop go into "no man's land"?

1.) A D flip-flop can be designed in several ways, but I think all of them are guaranteed to come out of metastability on the second clock pulse, if there is no timing violation.

2.) If the D input is metastable at the active clock edge, the output can go '0', '1' or metastable. It is a random function. It does not help if the previous stage goes out of metastability at the same clock edge.

This means that there is no guarantee to avoid metastability on the output of a two-stage synchronizer. The MTBF depends on the clock frequency. Altera recommends 3 stages for high frequency synchronizers.

 

[FvM]

Let me try to ask the questions I'm trying to understand a bit more plainly:
1.) If a flip flop's output goes metastable due to a timing violation, is it's output guaranteed to come out of metastability and accurately reflect the the input on the next clock tick, provided the new input to the flip flop doesn't create a new timing violation?

To emphasize the answer to your first question, that has already been given by others. Metastability get's evident only if it lasts at least until the output signal is read by another FF. That's why it's probability strongly depends on the clock frequency.

By cascading N synchronizers, the already small metastability probability is raised to the power of N. In many cases, the MTBF (mean time before failure respectively average time between two metastable events) will be larger than the lifetime of the universe, already with a two-stage synchronizer. But because cycle time is an exponent in the equation, you can also get imaginable time periods with high speed designs.


Below an Altera paper, that discusses the genesis of and calculation methods for metastability:
https://www.altera.com/literature/wp/wp-01082-quartus-ii-metastability.pdf