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Hi, I have experience about your question.
You should avoid making Vgs Vgd > 3.3v first.
If Vds > 3.3v, the L shoud be longer than min rule, three times is enough,because of hot carrier effect.
But power down is problem, It's hard to power down without any current because of reliability issue.
Hi DL:
1.I'm not sure which one is most apropriate, but as a designer, you need check more transmission line model ,the more the better.
2.yes
3.hspice
MIM Capacitor is the capacitor between two metal.
Some layers are dummy layer for MIM Cap.
For example, if the capactior is constructed between M8 and M7, then the M7 density check would exclude the CBM region
Fail-safe is used to detect High-Z state, I think you can use a pull_up RES, and design a circuit that when the input commod voltage is bigger than SPEC,the output is high.
Re: capacitor matching
Hi leo_02:
Thanks for your reply. It is also important to me.
Could you help giving particular description of the your answer? Maybe you can replace "blank" to "•" "×" or other symbols.
Using metal jump is another way to avoid antenna effect.
Example below:
••••••••••••••••••••••••••••••short metal 3
•••••••••••••••••••••••••••••via•••••••••via
••••••••••••••••••short metal 2•••••••••••long metal 2
•••••••••••••••••via••••••••••••••••••••••••••••••••via
•••••••short...
Re: layout of bandgap
I'm not sure which is better.
But in my chip, I use metal 1 to connect GND and metal 2 connect the emitter the tapout reslut is ok.
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