Fail-safe circuit in an LVDS Receiver

[malikmunish]

How can one implement Fail-Safe circuit for LVDS Receiver which is directly coupled. There are fail-safe circuits found for the receiver that is capacitively coupled. But, our requirement is fail-safe circuit for LVDS Receiver without capacitive coupling.

OR

Can anyone tell how to detect a zero differential signal received by the LVDS Receiver, while detecting random LVDS data?

 

[plusminus]

I don't know if you have something about it: For RS485 you use a bias circuit. Just a resistor from VCC to input, resistor (562?) between input/inv. input(130 ?, terminator) and a resistor (562?) from GND to inv.input

In this link they have an example of a failsafe LVDS Receiver.
**broken link removed** (page 3-4)

 

[avt]

the latter question depends on your comparator structure in the receiver - if you have a receiver which respects the hysteresis requirements of ieee1594 then you might adapt from that some kind of window comparator funtion which will alow you to detect a zero diff signal ...

at least this is one way to do it ...

 

[panyi]

Fail-safe is used to detect High-Z state, I think you can use a pull_up RES, and design a circuit that when the input commod voltage is bigger than SPEC,the output is high.