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Recent content by pamulurureddy

  1. P

    Cell library or Design kit for Cadence

    did you got the library.. pls share the info
  2. P

    USB specifications and working cores link and document

    USB specifications search for usb in a nutshell in google this is good
  3. P

    reg:synplicity information

    what are your requirements Added after 1 minutes: can tell more about synplicity dsp
  4. P

    Tool that generates layout from Spice netlist or Verilog code

    verilog to layout? ithink magama flow will from RTL GDS2
  5. P

    plz provide inputs for coming interview

    verilog vhdl clear idea of setup and hold time little idea about synthesis design flow
  6. P

    Recommend me ASIC design courses

    ASIC course asic means you have to do all from front end to backend
  7. P

    How to transport a design from Synopsis to Cadence?

    You migh want to check your lib... tim, cel, frame for synopsys, but lef, tlf, def for Cadence... i am generating standard cell with difft ext with respect to the customer
  8. P

    Next step after timing analysis

    you have to check through critical paths only
  9. P

    STA problem need help!

    n STA we go for best case analysis for Hold check and worst case analysis for setup check.
  10. P

    Question on ASIC Test

    DFT is diffirent and test engineers work is different.
  11. P

    Why clocks have 50% duty cycle in many designs ?

    Clocks problem to maintain the synchconisation we keep 50%
  12. P

    USB Host Simulation Model

    Yes there will be host model. i was working on c language host model and for simulation i use to write PLI routines Reddy
  13. P

    where can i get materials on PCMCIA bus interface

    Yes you can uplode it. or if possible you can send to my home mail id pamulurureddy@yahoo.co.in and let me know about the core. where can it available

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