Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

STA problem need help!

Status
Not open for further replies.

dolby.yang

Member level 4
Joined
Mar 2, 2005
Messages
73
Helped
10
Reputation
20
Reaction score
2
Trophy points
1,288
Activity points
1,862
in sta ,to do setup and hold check, we need to select wire load mode, but there usualy have worst wire load mode and best wire load mode.how to select this two mode to do setup and hold check?

thanks!
 

probably worst wire load model
 

thank you !
select worst wire load mode to check setup or hold or both?
 

this wire load model will be selected according design's area if u did not define explicitly.
 

u must use best operating conditions for hold checks and worst operating conditions for setup check. wireload selection is same for both setup and hold check. it is the libraries and operating conditions which decides whether u r selecting worst or best conditions.
 

sta requires real backend data ,not wireload model.
wireload model is only for synthesis
 

Hi

In STA we go for best case analysis for Hold check and
worst case analysis for setup check.
 

sandysuhy said:
Hi

In STA we go for best case analysis for Hold check and
worst case analysis for setup check.


thank you,i want to know the reason ,can u explain it for me?
 

setup time = clock cycle - max data delay
hold time = max clock delay(skew) - min data delay

With worst case condition, setup time can get most critical value,
With best case condition, hold time can get most critical value in mostly environment.
 

hyena_dale said:
setup time = clock cycle - max data delay
hold time = max clock delay(skew) - min data delay

With worst case condition, setup time can get most critical value,
With best case condition, hold time can get most critical value in mostly environment.

thank you! you are right.:)
 

try OCV (On Chip Variation) mode also
 

hi dolby,
In fact, wire load mode is based on statistic, so it has low accuracy for timing analysis excecially for hold check. So i think it is better to do hold check with RC information instead of WLM
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top