masai_mara
Advanced Member level 4
hi guys,
I need your help. I have got an interview coming up with an asic company for frontend design position.
I know VHDL quite well and also verilog. I have worked as a design/verification engineer for about a year and know about issues related to systhesis and simulation. but much of my experience has been working on fpga stuff. so please give me as many pointers as you can on what areas to target for preparation.
thanks for all your help.
I need your help. I have got an interview coming up with an asic company for frontend design position.
I know VHDL quite well and also verilog. I have worked as a design/verification engineer for about a year and know about issues related to systhesis and simulation. but much of my experience has been working on fpga stuff. so please give me as many pointers as you can on what areas to target for preparation.
thanks for all your help.