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Recent content by otis

  1. O

    Question insv- class copy method

    Hi Dave, Thanks for your reply. It helped me.
  2. O

    Question insv- class copy method

    Hi, I have a question in the copy method. I hope this is the correct forum Here is the code package test_pkg; typedef enum bit {rd, wr} typ_dir; typedef logic [15:0] typ_data; typedef logic [15:0] typ_addr; typedef class stream; class packet; static int next_ID...
  3. O

    RAM access (read/write)!

    Hi, I have to write a simple RAM acess(read/write) for ARM cortex M3 core. I need this for my test environment I think it should be very simple.I come from VLSI baground - I need a quick start on this .. Does any one give me some example code or links for example code. Thanks!
  4. O

    net balsting in verilog

    1) Yes it is valid 2) Generally should not cause any issue in front end. But, it is highly not recommended in normal conditions. You can find this recommendation in Cadence, Mentor Verilog reference manuals.
  5. O

    what is `celldefine in Verilog

    Hi, could anyone explain about `celldefine? What is it? and where it is used? Thanks!
  6. O

    ncxlmode - lib inclusion how?

    Hi I am simulating some Verilog models of analog circuits. I wrote TB in Verilog. Main analog blocks(DUT) are modeled manually. some primitives are taken from the library. I use ncxlmode to run the simulation. all the models which are modeled manually are included in the simulation. no issue...
  7. O

    what is golden in lec

    There are three types of netlist during design process. bronze,silver and gold. When you get bronze netlist is not the final one, still designer may expect changes in RTL. Silver more or less RTL is fixed but there may be some rework done at gate level. When you say golden netlist that means...
  8. O

    clock gating - implementing ICG cell

    clock gating I am going to add a clock gate in my design. There are many papers in the Internet says do not use clock gate logic directly instead use ICG - Integrated Clock Gate. But I dont know how to do this in RTL level. I found this cell in the technology library. But I am not sure how...
  9. O

    Baisic flip-flop circiut

    OK what are you studying? tell me your background. Then we will start discussing about this.
  10. O

    Baisic flip-flop circiut

    I can help you But i am not sure about this part of the question --------------------------- Input State 0 1 S1 S2 S3 S2 S2 S3 S3 S3 S1 Output Table Input State 0 1 S1 0 0 S2 1 0 S3 0 1 --------------------------- Can you post more preciously they way you got it? But some of your...
  11. O

    Interview Questions: How to find same contents in a FIFO

    :) I did not get it from anywhere I made it myself. I used visio to draw it.
  12. O

    setup and hold time....backend basics

    Great! This almost cleared my doubt.. Still need to understand few more things.
  13. O

    what kind of logic to choose?

    Yes, pass gates or trasmission gates are non-restoring circuit and it will pass what ever it gets in the input. Please find the attached image of trasmission gates.
  14. O

    Interview Questions: How to find same contents in a FIFO

    please find the attached image.. comments are welcome
  15. O

    setup and hold time....backend basics

    Hi Jeevan thanks! But I am looking for some deatils in termans of electrons / channel and so on. @lostinxlation :- could you tell me how it fights back?
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