otis
Member level 3

Hi
I am simulating some Verilog models of analog circuits. I wrote TB in Verilog.
Main analog blocks(DUT) are modeled manually. some primitives are taken from the library.
I use ncxlmode to run the simulation.
all the models which are modeled manually are included in the simulation. no issue there. But some models are using primitives which are part of the library that I include in the script.But the simulation sees the folder which I mention but they are not really included in simulation - I get error during elaboration.
Lets say library name is tsmc45nm. the primitives are located as follows
/tsmc45
_____/primitive_one
__________/functional/verilog.v
__________/layout/*
__________/schematic
__________/symbol
_____/primitive_two
__________/functional/verilog.v
__________/layout/*
__________/schematic
__________/symbol
_____/primitive_three
__________/functional/verilog.v
__________/layout/*
__________/schematic
__________/symbol
Please note that the Verilog file name is always same and it is called "verilog.v" but the module name in the file are different.
Here is my sim script
ncxlmode \
+noupdate \
+licq \
+access+rwc \
+define+SHM \
+incdir+../bench \
+incdir+../models \
+incdir+../sdf \
../bench/tb.v \
-y /blabla...lala/tsmc45nm \
+libext+.v \
-y ../models \
+libtext+.v \
this script gives following message
ncvlog: *W,LIBNOU: Library "/blabla...lala/tsmc45nm" given but not used.
And it later it produces error "design unit 'primitive_one' is unresolved" (also for other primitives)
Could anyone explain how to make the tool to get these library into simulation?
Thanks in advance!
I am simulating some Verilog models of analog circuits. I wrote TB in Verilog.
Main analog blocks(DUT) are modeled manually. some primitives are taken from the library.
I use ncxlmode to run the simulation.
all the models which are modeled manually are included in the simulation. no issue there. But some models are using primitives which are part of the library that I include in the script.But the simulation sees the folder which I mention but they are not really included in simulation - I get error during elaboration.
Lets say library name is tsmc45nm. the primitives are located as follows
/tsmc45
_____/primitive_one
__________/functional/verilog.v
__________/layout/*
__________/schematic
__________/symbol
_____/primitive_two
__________/functional/verilog.v
__________/layout/*
__________/schematic
__________/symbol
_____/primitive_three
__________/functional/verilog.v
__________/layout/*
__________/schematic
__________/symbol
Please note that the Verilog file name is always same and it is called "verilog.v" but the module name in the file are different.
Here is my sim script
ncxlmode \
+noupdate \
+licq \
+access+rwc \
+define+SHM \
+incdir+../bench \
+incdir+../models \
+incdir+../sdf \
../bench/tb.v \
-y /blabla...lala/tsmc45nm \
+libext+.v \
-y ../models \
+libtext+.v \
this script gives following message
ncvlog: *W,LIBNOU: Library "/blabla...lala/tsmc45nm" given but not used.
And it later it produces error "design unit 'primitive_one' is unresolved" (also for other primitives)
Could anyone explain how to make the tool to get these library into simulation?
Thanks in advance!