setup and hold time....backend basics

[otis]

Hi

Almost everyone knows what is setup and hold time is and how they are considered in Fmax calculation and so on.

I am looking for some answers in terms of physics.

Why there should be a setup and hold time need to be there.
Typical answer would be it is there to avoid metastability and violations and so on..

But I would know in terms of capacitance and why CMOS circuit fails to pick up the right data when setup or hold time violated. (with the details of mosfet devices)

Thanks in advance

 

[lostinxlation]

because a keeper has a weak feedback and the feedback inverter fights against the driver.

 

[jeevan.life]

Set up and hold time are specified because of slew or transition times I suppose....In practical you will not find a perfect square wave and every wave has some delay in rising to the data value...this depends on capacitance of the wire, gate and drive strength of buffer if any...Please correct me if i'm wrong

 

[otis]

Hi Jeevan thanks! But I am looking for some deatils in termans of electrons / channel and so on.

@lostinxlation :- could you tell me how it fights back?

 

[lostinxlation]

could you tell me how it fights back?

My suggestion is looking at the transistor level circuit of a flop or latch.
The input data is captured into a keeper in a flop/latch, where the keeper is made with a forward and a feedback inverter. When the input data flips, the cell driving the flop input and the feedback inverter in the keeper will contend and create a DC path. Since the feedback inverter has a higher resistance, the value in the keeper will settle to the new value quickly, but it still takes time. Setup and hold time are determined by how quickly the data in the keeper can settle.

 

[otis]

Great!
This almost cleared my doubt.. Still need to understand few more things.

 

[nandik01]

My suggestion is looking at the transistor level circuit of a flop or latch.
The input data is captured into a keeper in a flop/latch, where the keeper is made with a forward and a feedback inverter. When the input data flips, the cell driving the flop input and the feedback inverter in the keeper will contend and create a DC path. Since the feedback inverter has a higher resistance, the value in the keeper will settle to the new value quickly, but it still takes time. Setup and hold time are determined by how quickly the data in the keeper can settle.

Hay dude can you please explain me in some lower level(more detailed)...... im unable to catch what you are explaining but pretty sure that you know whats happening inside perfectly. ...... please reply asap...tnx