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Recent content by oly

  1. O

    contiki programming in cooja

    how to broadcast a packet from one node to another. i am not able to understand how to code this.please help me by sending a code.
    • oly
    • Thread
    • Replies: 0
    • Forum: Network
  2. O

    related to sram array

    hello, I am creating a 4x4 6T sram array and i want to know that 1) what will be the idle writing and reading time for which the word line should high for 6T sram? 2)whenever i turn on the wordline after precharge the bitline and bitline bar gets discharged frequently why?
  3. O

    how to measure voltage ina time period using hspice

    hello i want to know that how to measure voltage at a node at given period of time using hspice??
  4. O

    Sram array power dissipation

    I want to know that if i will create a 6T sram array of 2x2 then if i want to calculate the power dissipation then how can i do this? i know how to calculate the power dissipation for the cell. but i want to know that how to calculate power dissipation for the array means for the architecture...
  5. O

    Capcitance values for sram

    Thanks for your reply. we are working in hspice 1) How can we calculate bit line length? 2)what do you mean with input capacitance per bit cell. If according to you input capacitance per bit cell = wiring cap. + source drain capacitance + contact. Then how can we calculate wiring capacitance as...
  6. O

    snm calculation of sram array

    hello. I want to know how to calculate snm for complete architecture??? and then for sram array?
  7. O

    Capcitance values for sram

    I just want to know that what should be the value of bitline capacitance and bitlinebar capacitance.
  8. O

    Capcitance values for sram

    Hello, I am simulating a 16x16 sram array(6T) at 45nm technology but i am confused about the value of capacitances of bit line and bit line bar.please help
  9. O

    write and read column circuitry of 6T sram

    i want to know how the read and write column circuitry connected in sram cell. and which circuitry are included in read and write column circuitry? thanks
  10. O

    Static and Dynamic Power dissipation calculation in EDA tool

    How can we calculate total power of any circuit in hspice??
  11. O

    sram architecture and its peripherals

    can you please give me the lik from where i can get the complete architecture?
  12. O

    sram architecture and its peripherals

    sir i want to know how the decoder circuitry and sense amplifier (different parts) are connceted with a 6T sram cell. i want internal structure of every parts rather than block diagram.
  13. O

    sram architecture and its peripherals

    i tried google but cant find internal structure for its peripherals.can you post the structure for my reference?
  14. O

    sram architecture and its peripherals

    I want to create a complete 6T sram architecture with all its peripherals (row decoder,column decoder,sense amplifier etc.). using hspice . i want to know the schematic of 6T sram with its peripherals.
  15. O

    Related to capacitance

    its very obvious typing mistake sorry for that, I test nmos in hspice and i found that drain voltage is inversly proportional to capacitance and gate voltage is directly proportional to capacitance? Is the analysis correct or not? Now can you give me the answer?
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