Capcitance values for sram

[oly]

Hello,
I am simulating a 16x16 sram array(6T) at 45nm technology but i am confused about the value of capacitances of bit line and bit line bar.please help

 

[erikl]

Confused? Too low or too high for 16 columns, including driver?

 

[oly]

I just want to know that what should be the value of bitline capacitance and bitlinebar capacitance.

 

[erikl]

Estimate it:

(input-capacitance_per_bit-cell * no_of_columns) * (1+d) + length_of_bit-line * 0.15 fF/µm

d = bit_line_driver_output_capacitance / bit_cells_input_capacitance ≈ 1.2

0.15 fF/µm is the typ. intermediate interconnect (M2) capacitance per µm length, including fringe part. It doesn't change very much with process size, s. e.g. the ITRS Interconnect_2011Tables, Table INTC2, lines (M) 60, 63 & 64.

 

[oly]

Thanks for your reply. we are working in hspice
1) How can we calculate bit line length?
2)what do you mean with input capacitance per bit cell. If according to you input capacitance per bit cell = wiring cap. + source drain capacitance + contact. Then how can we calculate wiring capacitance as we are working in hspice?
3) And there are two bit lines in each sram cell. Then why input capacitance per bit cell multiply with no. of columns and not with no. of rows??

 

[erikl]

1) How can we calculate bit line length?
2)what do you mean with input capacitance per bit cell. If according to you input capacitance per bit cell = wiring cap. + source drain capacitance + contact. Then how can we calculate wiring capacitance as we are working in hspice?

This has nothing to do with your simulator tool (hspice).

If you have a layout, you can extract all these capacitances. If you don't have a layout, you still can estimate these caps according to your schematic, and to the advice given above.

3) And there are two bit lines in each sram cell. Then why input capacitance per bit cell multiply with no. of columns and not with no. of rows??

Of course 2 bit lines. Usually, bit-lines are shown vertically, i.e. they supply the bit cells in a column, s. e.g. this SRAM lecture, Slide 4.