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Re: FPGA Programmer
Hi
For prgramming FPGAs, there exists various modes like : 1) JTAG 2) Serial Slave etc. more information on them you can find on the website of Xilinx.
Xilinx also provides cables for programming, in case of development boards they come along with. However for your own...
the general technique that i have come accross for the power supply of the kind you are stating is as follows: -
a buck regulator based low voltage power supply which is followed by a chopper and multiplier section. here the adavnatge is that you can use 1 kV fast recoverry diodes which are...
Hi all,
I have tried to implement fast DCT and fast IDCT in C by using separable property and taking 8X8 block at a time of an image. But results are a little bit strange. I see verticle and horizntal lines throughout the image. these lines seems to be obvious from the fact that I am taking one...
Re: Filtering using matlab
yes I want to change the unwanted points to zero.
How is that possible i mean actually on time scale (in data points with me) the duration between the two sharp pulses is .5 us. and i dont understand how to identify and draw its FFT so that I can identify the...
Filtering using matlab
Hi all,
I have a waveform as shown below, I have clearly mentioned in this waveform the imformation which is neccessary for me. Now I want to remove all other noise and wish to see only these sharp pulses without noise.The data is available with me and I want to use...
Re: Digital Timing Concepts
Hi all,
It was nice to see your valuable replies.
Could anyone upload the manuals of design compilers, or if they are available on web then could anyone give me link for it. I tried to search it but could not find.
thanks and regards,
Digital Timing Concepts
Hi all,
Could any one suggest me book or www link to understand the timing concepts related to digital system design(synchronous, asynchronous etc) , specifically those concepts which we do normally face while designing FPGA based systems.
thanks and regards,
hi fakeha_s,
But it didnt help me to understand where, why and how should i specify timing constraints. could you send me a link from where i can get more abt it
thanks and regards,
Nitin
Hi all,
I am working xilinx's tools ISE 6.1, I have simulated various VHDL codes using ModelSim and Aldec simulator. I have successfully synthesised them too with ISE but I dont know about timing constraints, could anybody refer me tutorial on it and associated terms like : clock to pad and pad...
Hi all
Can anybody tell me or give reference to the site which can describe the capabilities of Embedded development kit from Xilinx which used with Virtex 4 and Virtex 2 Pro ( ie basically PowerPC based FPGAs)?
Please note that I have seen various tutorials which deals with the implementation...
No it isn't like there is no need to connect to xilinx server to synthesize your code in ISE web pack, basically ISE webpack can be downloaded from xilinx site and one can synthesiz a limited number for CPLD/FPGAs devices from xilinx while in case of ISE foundation one has to buy the tool and it...
Re: Help!!!
hi,
thanks for all the replies..
i have also sorted out a solution for the problem.
the problem was actually a single process cannt not detect both rsising as well as falling edge pf a signal. this is where i was mistaking, but now the thing is clear and i m also putting one...
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