Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
iec 60958-3
I am searching for the definitions of the sample rate accuracy Levels for spdif / IEC 60958-3. Does anyone knows them or knows where i can find the definitions ?
Many thanks
nkef
synopsys designware unable to resolve reference
I instanciated a multiplier with the "*" symbol in the following entity
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity mult is
generic ( inst_A_width : integer := 8;
inst_B_width : integer := 8
);
port ( a : in...
unconnected input synthesis
I finally removed them by running:
remove_unconnected_ports -blast_buses [find -hierarchy cell {"*"}]
after the elaborate command.
With unconnected_ports i got warnings when i was trying to export the design to vhdl.
warning: unconnected hierarchy pin
Sorry i forgot to mention, i tried to remove them with:
remove_unconnected_ports [find -hierarchy cell {"*"}]
but nothink happens :(
remove_unconnected_ports
I am getting the
Warning: In design 'codec_width16', port 'data_a[5]' is not connected to any nets. (LINT-28) , because some of the input ports dont drive any nets, how it is possible to remove them in dc?
Many thanks
Nkef
The Cell from the DesignWare library is instantiated properly after the elaborate command, but after the compile, this cell is replaced with primitives instead of the full adder cell from the asic library.
I am using Design Compiler, width tsmc 0.13 Asic library.
The tsmc library provides full adder cell but Design Compiler is not using it.
I instantiated a full adder using the component instantiation as descripted in Designware User Guide.
library IEEE, GTECH;
use IEEE.std_logic_1164.all;
use...
I am trying to create a library from vhdl source with Synopsys Design compiler.
I am following these procedure:
i enter the directory where vhdl source is
mkdir my_lib
dc_shell-t
define_design_lib my_lib ./my_lib
analyze -format vhdl -lib my_lib ./libsource.vhd
then it is supposed that a...
I need to draw some schematics at gate and trasistor level, is there any tool that i can draw some good-looking schematics and export them to a scalar graphics format like svg , emf ? I am trying to avoid ending up using corel or somethink like it, it is very time consuming :cry:
Graphical VHDL Editor
I am looking for a Graphical VHDL Editor. I have build varius VHDL modules and i want to create multiple instances of them and connect them in pure-structural manner at top-level. I wish to avoid instantiating them by hand because it is confusing and error prone :cry:. I...
Mathematics Dictionary
I am looking forward to buy a mathematics dictionary, i have found some after little search on the web like the:
The Concise Oxford Dictionary of Mathematics...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
