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Recent content by niuniu

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    How to simulate a SystemC design with Cadence NCsim?

    ncsc cadence tutorial Now you can use verdi to dump waveform without write any sc_trace. it is just like using $fsdbdump in verilog, just point the starting point and level you want to dump. for how to simulate or co-simulation, I belive the cdsdoc has fully document the detail. if you are...
  2. N

    verilog testbench book

    writing testbench with system verilog is also good. with system verilog, you have more freedom to write better testbench.
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    who have these two document

    Seems like the user manual of some EDA tools. It should comes with the software.
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    Learning VLSI at an institute

    A query friends what a pity. but why you must choost VLSI.
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    Which country has best opportunities (work and Pay) in VLSI

    average salary for vlsi professionals in us How about the compensation?
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    Is there a algorithm which can calculate matrix multiply? H!

    Is there a algorithm which can calculate matrix multiply? depend on how fast your want, and how many resource the chip can afford.
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    Help required regarding Linux...........

    if your company choose redhat, you better use the same. Fedora or centos
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    Why latches are not preferred in any design?

    Latch -reg. the main reason is lack of EDA tools to support large design.
  9. N

    Ideas for adding functionality to ASIC project

    asic project idea check about opencore, many example to start with.
  10. N

    [REQ]SystemVerilog or VMM material

    VMM can be found in VCS install dir. there are two books about system verilog in Ebooks download section.
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    Upcoming PSL training @ CVC, Bangalore on 15th Oct

    what is the future trend of PSL vs. SVA
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    Need description of Verdi shorcuts

    Verdi shorcuts if you have the tool, the help is very good. there is an video training on www.demosondemand.com which can be an good starting point. I found it is not easy to ready any training on how to manipulate the GUI unless you try it yourself.
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    LEC problem on DC 2006.06 ?

    compile_ultra no_autoungroup this is because dc uses many high level synthesis which makes LEC very difficult. one way is to let DC write out svf file and use formality. but we still found there is abort. have you use compile_ultra? if so, try to use these options like compile_ultra...
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    What's the best VHDL/Verilog/SystemVerilog editor?

    systemverilog eclipse plugin Where to find the SV mode for emacs?
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    How to use VCS to watch the internal memory in my design?

    vcs memcbk use latest verdi from Novas company, they can infer the memory content based on read/write history. very cute.
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