How to simulate a SystemC design with Cadence NCsim?

[master_picengineer]

Hi all,
Can someone explain how to simulate a SystemC design With Candence NCsim.
Thanks.

 

[xuxia]

ncsim systemc

please use ncsc

 

[master_picengineer]

irun cadence

Dear xuxia,
Could you please through more ligth on ncsc and explain how to simulate systemc with it.
Thanks.

 

[funzero]

cadence irun

ncsc will compile the systemc file into simualtion database,than you can use ncelab ncsim

 

[sanjay11]

cadence irun -f

Use the 'irun' utility provided by cadence.
it will pick up the files as per extenstion and compile them.
You need to mention -sysc option alogwith irun on command prompt for systemC.

 

[samuraign]

ncsc systemc

I heard that "sc_main" can not be used with NC-SystemC.

Can any body tell me what will be the advantage in using NC-SystemC for simulating a pure SystemC simulations.

Is there any possibility to avoid dumping waveform in VCD format by sc_trace and use NC-SystemC to get waveform.

Please share your knowledge on NC-SystemC
(1) benefits & Advantage(Apart from co-simulation)
(2) usage

 

[niuniu]

ncsc cadence tutorial

I heard that "sc_main" can not be used with NC-SystemC.

Can any body tell me what will be the advantage in using NC-SystemC for simulating a pure SystemC simulations.

Is there any possibility to avoid dumping waveform in VCD format by sc_trace and use NC-SystemC to get waveform.

Please share your knowledge on NC-SystemC
(1) benefits & Advantage(Apart from co-simulation)
(2) usage

Now you can use verdi to dump waveform without write any sc_trace. it is just like using $fsdbdump in verilog, just point the starting point and level you want to dump.

for how to simulate or co-simulation, I belive the cdsdoc has fully document the detail.

if you are using pure SystemC right now, maybe you do not need ncsc since it cost license fee. it was said the the native compiler of ncsc is faster than open source version, but it may lack of debugging GUI like VC.