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Recent content by nitin mukesh

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    [SOLVED] MIM CAP UNbalance

    The above problem is solved by using od to metal 8 vias on both the side of the mimcap to balance it.
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    [SOLVED] MIM CAP UNbalance

    both the CTM and CBM are of Metal 8
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    [SOLVED] MIM CAP UNbalance

    I am connecting my mim cap to one of the drain of a MOS. As I connect the Plus side of the mim cap to the drain of the MOSFET, I get this error "Unbalanced structure is not allowed." STAMP unBal_CTM_M8 CTM A.R.MIM.1:M8:A ANTENNA -gt 0.000000 A.R.MIM.1:M8:A M8i A.R.MIM.1:M8:L262206 STAMP...
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    Mim cap not detected in layout in tsmcn65

    I could, but then I will not be able to do RC extraction without lvs running. 1673504912 Any way we can realise it.
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    [SOLVED] RC Extraction

    The above problem is solved by removing the library which was clashing.
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    Mim cap not detected in layout in tsmcn65

    We are facing a few issues 1. Regarding the mimcap. As I run the LVS having only mimcap in schematic and layout, I get an error message stating: *ERROR* Device 'mimcap(Generic)' on Schematic is unbound to any Layout device. *ERROR* UnBound devices found. I have gone through the...
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    [SOLVED] RC Extraction

    I also thought the same. But I have created a library where I have attached tsmc65 and used tsmc 65 nmos in schematic and as well as layout. I have used a single transistor of tsmc 65 where and why the quantus QRC is checking for other librariies is the quetion. Any idea how can i check that...
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    [SOLVED] RC Extraction

    I understand that but I am not understanding where it is getting mixed as the assura tech file, I am using is TSMC65. Do you have any idea why it is considering other PDKs ?
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    [SOLVED] RC Extraction

    Hey Everyone, I am using Cadence and for RC extraction I am using ASSURA Quantus. 1. We can run the RC extraction for the .sp (spice) format. 2. But whenever we try to run the av_extracted view, we get an error stating: The error log file & assura quantus setup screenshot has been...
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    tsmc n65 ( purpoe of layers: IP / DIODMY / PDK )

    Hey Every one, I cannot find the purpose of these layers in a diode ndio_25 in tsmc 65. 1. IP 2. DIODMY 3. PDK Please comment on the purpose as I am interested in making a diode from scratch are they required in the custom layout of the diode and if yes how can I use them?
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    [SOLVED] Photo Diode Design in cadence using TSMC 65nm

    Hey Hey, I would like to know one more thing. I am trying to make a photodiode so I have taken the standard diode in schematic ndio_25 but in the layout, I want to make it custom so, I have created the NP region and provided the contacts in NP region and in the P substrate I have made contacts...
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    [SOLVED] tsmc n65 vias

    Hey Everyone, I am designing a circuit and I would like to know certain connections or VIAS which can be used. Q1. To connect it to Pwell I am using M1_SUB there is no M1_Pwell am I right in choosing M1_SUB ? Q2. I would like to have a connection between M1 and the NP region but there is no...
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    [SOLVED] Photo Diode Design in cadence using TSMC 65nm

    Hey I am new here and i wanted to design a photo diode for my CMOS image sensor. Q1. Can I use the standard diode and since I wanted my photodiode to expose to the light so i will remove the OD layer will that solve my problem? what else do i need to take care of since i want that the...

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