[SOLVED] Photo Diode Design in cadence using TSMC 65nm

[nitin mukesh]

Hey I am new here and i wanted to design a photo diode for my CMOS image sensor.

Q1. Can I use the standard diode and since I wanted my photodiode to expose to the light so i will remove the OD layer will that solve my problem?

what else do i need to take care of since i want that the photodiode should be exposed to light which layers should i use?

 

[dick_freebird]

Well, how good a photodiode do you want it to be?

If you want to see state of the art, look at CMOS image sensor papers for details like how they suppress surface recombination and access to surface traps that make RTN, maximize collection within while excluding from outside pixel extent, etc.

 

[shlooky]

Hi there,

Every semiconductor diode is a photo-diode.... The ambient light will affect the saturatiom current of any PN junction. So in order to get a photodiode from standrad CMOS process (like your TSMC 65nm) you need to expose the silicon die to the light. This will, however, affect all the exposed components on chip....

OD layer is in other words just a symbolic layer for area of thin oxide where the implanted ions will land into the silicon rather then get trapped in field oxide (FOX) and be inactive.
Removing OD layer in your layout design will result in a structure without "active area" or "thin oxide" and therefore without P or N areas. If that layout passes your DRC checks, of course... not sure whether the contacts can be placed on FOX...

Shlooky

 

[nitin mukesh]

Hi there,

Every semiconductor diode is a photo-diode.... The ambient light will affect the saturatiom current of any PN junction. So in order to get a photodiode from standrad CMOS process (like your TSMC 65nm) you need to expose the silicon die to the light. This will, however, affect all the exposed components on chip....

OD layer is in other words just a symbolic layer for area of thin oxide where the implanted ions will land into the silicon rather then get trapped in field oxide (FOX) and be inactive.
Removing OD layer in your layout design will result in a structure without "active area" or "thin oxide" and therefore without P or N areas. If that layout passes your DRC checks, of course... not sure whether the contacts can be placed on FOX...

Shlooky

Hey

Hey, I would like to know one more thing. I am trying to make a photodiode so I have taken the standard diode in schematic ndio_25 but in the layout, I want to make it custom so, I have created the NP region and provided the contacts in NP region and in the P substrate I have made contacts using M1 to substrate contacts/vias named it respectively "n" & "p".

While running the LVS I am getting the error ndio_25 is unbound to any layout device.
UnBound device found.

can you help me where I am going wrong in this?

 

[shlooky]

Hi there,

there is probably some symbolic layer that identifies ndio_25 for the extractor.
I would take standard ndio_25, flatten it (Edit -> Hierarchy -> Flatten), so you have all the layers needed for a diode and then stretch the polygons to desired dimensions with DRC checks...

Shlooky