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The dimension of the output is a range 3 to 8, the max size of the array is 8 x 8. A xor_gate is a xor gate. It doesn't work means it's not recognized and it is red underlined an error will be occurred if I synthesize it.
I have a matrix with rows and columns of XOR, n x m. In the first output I want to assign the output with a signal to the first row.
How I am going to do that?
type matrix is array(0 to n-1) of std_logic_vector(m - 1 downto 0);
signal out_vec : matrix;
begin
for i in 0 to n-1 generate...
No, I think the whole structure is wrong. We need one more row of the next two operands and not three totally. Lets say we have three in the first row { c, b, a} and in the next row { e, d} and then I should connect it all together to the CPA. But first I am gonna do it by hand. Just don't spend...
Yes is not correct I checked with other values but doesn't work. Well it works with most of them in the simulation but not with alternative values. I am trying to figure out an alternative structure. I run it by hand only with 15 values but not for others.
Thanks buddy for the food for thought! It was actually 2 HA's below S4. After trying a lot of solution models I found the right answer. I provide the solution for everyone who has this problem with odd input operands.
There is not an error in the synthesis, there is structural problem of the carry save adder. The only error message I get is the assertation of the simulation. The result should be 75 and it is 91.
I am getting an error in my design with Vivado and it is in the CPA last level. It means I am doing something wrong in my design.
How to connect the sum(4) in the output? I am getting a different result (91 instead of 75), what I am doing wrong?
My code is huge, each operand has 4 bit input, its a carry select adder. I need to fix it because I have to use the for - generate statement. Yeah you have right. The input must be something, otherwise won't work.
Hi there, I have a gradually input-upwards multiplexer. I designed a general 3 bit input multiplexer with one select input and one output. My question is, that in the first level MUX_0 from the 3 bit-input I am using only one bit, so accordingly
MUX_0 = 1 bit input usage
MUX_1 = 2 bit input...
I solved the all the problems with Xilinx, but I don't understand, why the file can be compiled directly with Modelsim using exactly the above implementation without an error but in the synthesis will not work?
I used this code for experiment, it has almost the same structure.
procedure xor_delay(
signal a_in : in std_ulogic;
signal b_in : in std_ulogic;
signal sum : out std_ulogic) is
begin
wait for 2 ns;
sum <= a_in xor b_in;
end...
I am a new with VHDL coding and I have some issues with the wait statement with quartus. With Vivado it works fine no problems with the compilation. First of all is "wait for 1 ns; " synthesizable ?
I am trying to compile the design and it fails as predeclared. Then I found and example from the...
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