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verilog project code
Emacs is not easy to use.
I used source insight for C and C++ programming. but is does not support verilog.
I hope I can find a tool as powerful as Source Insight and support Verilog
Thanks
I don't think you can figure out the die size from gate counts. There are several ways which will affect your die size:
1. Row utilization.
2. IO to core distance(X and Y).
3. Core to Block distance.
4. More....
BTW, it depends on pad limited or core limited
Mutou
Re: help:design clock 4MHz
Do you need 4Mhz clk 50% duty? If it is not, it is very easy, you can use state machine to divide 20Mhz clk by 5 then get 4Mhz clk. Please email me if you need more detail help.
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