Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by Mina Magdy

  1. M

    verilog code of 8 dct architecture

    i think you should take care that when you add two signals with data width [0:n]the o/p should be [0:n+1]
  2. M

    What is the most important SV and UVM?

    if you have any knowledge about object oriented it will make it easy to learn system verilog, if not it will be helpful if you read more about Object oriented concept but not so deep only concept and then system verilog read "LRM 1800-2012" . about UVM there is site called " Verification...
  3. M

    immediate assertion in systemverilog (SVA)

    Hi I would like to know 1) what is the working phases of immediate assertion? 2) does immediate assertion have any use other than asynchronous checks? 3) could i write immediate assertion inside program block as i think it will be concurrent assertion not immediate ? 4) does i have the ability...
  4. M

    SDF entries and their correlation with timing?

    Hi vaidyseenu, SPF(standard parasitic format) describes interconnect delay and loading due to parasitic resistance and capacitance. https://iroi.seu.edu.cn/books/asics/Book2/CH17/CH17.4.htm look at section 17.4.1 1)the Setup and hold are usually determined by using the SDF file on Timing tool ...
  5. M

    AXI master and slave design

    hi kindly if you have reaches any material other than the specs for axi i would be pleased :-D
  6. M

    Verilog multi dimensional array

    i have faced the same problem before but when i declare both as a packed array but in unpacked array error may due to trying to equaling or comparing the two arrays or display the hole array not one element a time.
  7. M

    do we need a fifo when read clk freq is greater than write clk freq?

    i think you have different cases: 1-same frequency and both clock are synchronous --> no need to any type of synchronization but you may need fifo depending upon requirnment. 2-same frequency and asynchronous --> you my need to use synchronization circuit which is a simple 2 or 3 flip flops...
  8. M

    Asynchronous FIFO verification

    Hi all i have designed an asynchronous FIFO and i would like to verify it but i am little confused what technique is better using assertion based verification or using normal simulation based verification(normal test-bench) . i would be glade if you could help me :-)
  9. M

    synchronization across clock domain

    but what happens if i face a case of a read and write in the same time will the ram read or it will write i know i will not even read or write in the same address at the same time but i am talking about the address selector on the ram
  10. M

    [SOLVED] how can i read from memory

    hi can i read from the memory after the positive edge clock ? i mean set the address after clock edge and having the o/p after normal read delay , i answer cause i found on SRam architecture sense amplifier which depend on clock during read and write ,and on other hand i can read after clock on...
  11. M

    synchronization across clock domain

    thanks for replay actually i search about it but what makes me confused is how the FIFO can respond to two different clock as i know we can use the SRAM as FIFO and SRAM is driven by only one clock.
  12. M

    synchronization across clock domain

    i have a question on how to connect two module with different clock ? i know i can use hand shacking or Circular FIFO but i want to know how it work and how to avoid metastability between two systems ? thanks in advance
  13. M

    [ HDMI ] specification

    thank you this is helping me a lot :-) but do you know any online course for explaining the HDMI but for Design and verification purpose
  14. M

    [ HDMI ] specification

    Hi i would like to know from where can i download HDMI 2.0 specification and if it is possible could any one help me with any reference for HDMI 2.0 i need it for verification purpose
  15. M

    Pipelining on AHB Protocol

    Hi i have a little confusion on the AHB Protocol and i need help. 1) why we use a delayed version of HMASTER[3:0] on the HWDATA MUX (the multiplexer that used to connect the data bus of master to the slave) 2) i know that we keep the pipelining on AHB Protocol by delay the data(HWDATA) one...
See more

Part and Inventory Search

Back
Top