synchronization across clock domain

[Mina Magdy]

i have a question on how to connect two module with different clock ?
i know i can use hand shacking or Circular FIFO but i want to know how it work and how to avoid metastability between two systems ?
thanks in advance

 

[barry]

the simplest approach is to use a two-flip-flop synchronizer. If you do an internet search there is lots of information about this and other synchronization methods.

 

[Mina Magdy]

the simplest approach is to use a two-flip-flop synchronizer. If you do an internet search there is lots of information about this and other synchronization methods.

thanks for replay
actually i search about it but what makes me confused is how the FIFO can respond to two different clock as i know we can use the SRAM as FIFO and SRAM is driven by only one clock.

 

[barry]

thanks for replay
actually i search about it but what makes me confused is how the FIFO can respond to two different clock as i know we can use the SRAM as FIFO and SRAM is driven by only one clock.

DUAL PORT SRAM is not necessarily driven by one clock, and FIFOs are generally built around DUAL Port RAM.

 

[Mina Magdy]

DUAL PORT SRAM is not necessarily driven by one clock, and FIFOs are generally built around DUAL Port RAM.

but what happens if i face a case of a read and write in the same time will the ram read or it will write i know i will not even read or write in the same address at the same time but i am talking about the address selector on the ram

 

[barry]

That's exactly why you use a FIFO, so that you can read and write independently and simultaneously. You need to learn a bit about dual-port RAM; they have independent address and data busses.

 

[layowblue]

Usually your FIFO controlling logic should output signals like near_empty, near_full. These indicators should be taken into account in designing your overall flow control in your system.