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Recent content by metuo_abeo

  1. M

    Autozero opamp

    Hi, Why this autozero opamp uses 4 capacitors instead of 2? I also attached the schematic of these opamps. Thanks!
  2. M

    Folded cascode Opamp

    Has someone another opinion?
  3. M

    Parasitic capacitors between clock wires? (analog layout)

    Thank you for your answer! So, my point (to add some parasitic capacitors in the schematic between the clock signals or between the input signal and clock signal) it's not a good idea.
  4. M

    Parasitic capacitors between clock wires? (analog layout)

    Hi, I want to make the layout for a sample&hold circuit that involves the autozero technique. My question is how to avoid possible dc coupling (and other effects like cross-talk) between these signals (non-overlapping signals). It's a good idea to add some parasitic capacitors in the schematic...
  5. M

    Pseudo-differential CMOS Switch Driver

    Hi, I want to use this CMOS switch driver in order to obtain 2 non-overlapping clock signals by using as input a 'vpulse' source from analoglib (Cadence Virtuoso). Could someone help me to understand how this circuit works and why is it called 'pseudo-differential? My assumption is that using...
  6. M

    Folded cascode Opamp

    Thanks for your answer, but I didn't understand the concept of 'guard', could you describe it? Also, the bias current chain is formed of M6, M7, M5, M18, and M20?
  7. M

    Folded cascode Opamp

    Hi, I want to simulate this schematic which is a folded cascode opamp with 2 stages for a higher gain and a Miller capacitor, but I don't understand what is the role of M20 and also why the M12/13-M14/15 gates are connected together. Could someone help me to understand this schematic step by...
  8. M

    Low offset voltage auto−zero stabilized CMOS operational amplifier

    Why should I bias a gate of MOSFET? Theoretically, it should be 0 (regarding the current). Your point is: small bias current + large gate resistance => the necessary voltages to control the MOSFETs?
  9. M

    Low offset voltage auto−zero stabilized CMOS operational amplifier

    Hello guys, I have to design a low offset voltage auto−zero stabilized CMOS operational amplifier and I started to analyze some existing implementations. I found this one, but I don't understand what are the bias pins (in left, bias 1/2/3/4) and what is their use in the schematic. This internal...
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