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Recent content by mc&fpga

  1. M

    data logger storage devices ?

    why you don't use the sdram memory as you know it uses in pc and for life guarantee .
  2. M

    How to fix block in par timing and add new blocks manually in ISE?

    i had the vhdl block that worked in a project but i add it to new project it can't work correctly and i think this problem happen in par so how can i fixed that block in par timming and how can i add new blocks manully.what's the best idea?
  3. M

    Please help me with designing a bus bridge in CPLD

    Re: bus bridge in CPLD as i see from your note, you want and you can control sdram in speed of 133 mhz,and interface the data to another bus,so you need an asynchrounse memory in your dsp processor or dma protochol in your dsp processor to control the speed of i/o bus in low speed,
  4. M

    [clock] 24Mhz from 50Mhz.

    ya,xilinx architecture wizard help you to make that dcm.
  5. M

    Please help me with designing a bus bridge in CPLD

    Re: bus bridge in CPLD ya,the dsp processor like ti c6000 and youranalog device processor like adsp have some peripheral to control the sdram or ddr bus,and they are cheap way to connect the memory and other bus(like ethernet), ya in some boards only for i/o buffering and implement other...
  6. M

    Please help me with designing a bus bridge in CPLD

    Re: bus bridge in CPLD as isee ,you want to communicate sdram and other bus like usb,... as you know you need a sequncer for controlling the refresh timiing of sdram and the another sequncer for controlling the bus timming like usb or ethernet, you will have problem to use coolrunner and...
  7. M

    Converting verilog RTL to verilog NETLIST

    hi, isthere any way to interpret the vhdl(synthesized code) netlist to rtl code?
  8. M

    How to introduce 2+ architectures and use one in XST?

    Re: XST operation yes,this happened in synthesizing with vhdl code Added after 1 minutes: yes,this happened in synthesizing with vhdl code
  9. M

    How to introduce 2+ architectures and use one in XST?

    xst configuration statements hi, how can we interduce two or more architecture for one project and select one for synthesize,, the other architecture that they weren't used has any effect in synthesizing? what's your idea? thanks
  10. M

    diffrence between commercial and industry

    hi is there any diffrence between industry and commerxcial pcb? for example when we say the board is industry or commrcial ? only the component used in that board say that or the pcb and type of the fiber and ..
  11. M

    guidance about designing the board more than 4 layers

    Re: quidance about designing the board more than 4 layers hi,thanks yes,they are some electronic rules for clock and vcc,& buut i need more details and proffesional about these rules,for example: if we use A/d or D/a how should we connect DGND and AGND like these, do you know articles about...
  12. M

    guidance about designing the board more than 4 layers

    hi who has experience in designig thge pcb for more than layers, who knows a site or articles about the attentions in this designing. for example which layer should be gnd and vcc if we have more than 3 vcc what should we do?about clk and ok,thanks
  13. M

    connect with parallel port in winxp

    how can i connect with parallel port in winxp,is there any sample code in vc++ or any idea about that?
  14. M

    Looking for example projects with MSP 430 in C language

    MSP 430 where can i find more sample project with c language by msp 430 microcontroller,and Iar software?
  15. M

    serial port and ppi in windows xp or 2000

    i want to use serial port parallel port in windows 2000 or xp how i can use them with vc++ any idea or experience about those?

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