How to introduce 2+ architectures and use one in XST?

[mc&fpga]

xst configuration statements

hi,
how can we interduce two or more architecture for one project and
select one for synthesize,,
the other architecture that they weren't used has any effect in synthesizing?
what's your idea?

thanks

 

[echo47]

xst select architecture

What do you mean by "architecture"? Perhaps clarify your question with an example.

 

[yjkwon57]

Re: XST operation

Maybe, you are using VHDL for your project.
Then, you can use the configuration specification.
It is something like a conditional compiler directive.

 

[mc&fpga]

Re: XST operation

yes,this happened in synthesizing with vhdl code

Added after 1 minutes:

yes,this happened in synthesizing with vhdl code

 

[bibo1978]

Re: XST operation

Ok here you are, if you are using two architecture in sperate files XST will take the first file you enter in sequence the otherfile will not be included in the tree you will find it above the project tree. However if the architectures are in teh same file XSt will just take the last architecture unless it is commented with--synopsys translate_off.

That's all folks

 

[dBUGGER]

XST operation

Hi,
Configuration statement is meant for what you want. Please refer any text book on VHDL and start reading about configurations. You can have any no. of architectures for an entity and associate any one for synthesis and simulation with the help of configuration statements. Configurations provide many more things. Read text to get the best result.

Best Regards,

 

[eeeraghu]

Re: XST operation

Hello,

I have done the synthesis part in Xilinx using XST, but for the implementation it do requires NGC file or NBD file, but i did not get the file, from where i have to look for the file,

Thanks
Regards

 

[tkbits]

Re: XST operation

Are you getting other errors?
Other kinds of errors can prevent the generation of these files.
Scroll backwards in the output window to see other errors.

 

[bibo1978]

Re: XST operation

if you have no error in the synthesis report then check out that you are not enabling "generate RTL schematic (only) option".