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Recent content by manosan

  1. M

    spartan 3xc3s4000 daisy chain help required

    I dont think so.. how will you program PROM then... Wht i know is, the connection should be connector - prom - FPGA1 -FPGA2 TDI is the config bit input... Also the TDO of last FPGA should be connected back to connector.. There is some issue related to that as well...
  2. M

    Please guide to me for VHDL coding

    This might be helpful for you http://esd.cs.ucr.edu/labs/tutorial/
  3. M

    What are the main specifications of VHDL core ?

    Re: what is vhdl core Any working code can be called a core.... Xilinx ISE has some inbult IP core such as memory controller,FIFO,multiplier etc
  4. M

    Is this a good way to get double-edge clocking in CPLD

    But I guess in effect you have two latches... one working at pos-edge and other at neg-edge...
  5. M

    rectangular signal in VHDL

    Is it like you need rectangular signal as output of DAC ?
  6. M

    spartan 3xc3s4000 daisy chain help required

    Hi, I was looking at your schematic.. I found two confusing signals... where does JTAG-TDO and JTAG-TDI go... The connections for daiy chaining is clearly given in Spartan3 datasheet or you can find configuraton details in Xilinx website..
  7. M

    advantage of fpga application??

    FPGA has features like DCM, Block RAMs etc which will be useful in designing an FFT. These are not there in CPLD.
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