Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by mahanthesh

  1. M

    What are the pros & cons of starting career in ASIC back

    Re: Doubt abt future Thanks truebs, Thanks for the reply
  2. M

    What are the pros & cons of starting career in ASIC back

    Doubt abt future Hello friends, I wanted to know what are the pros & cons of starting career in ASIC back end from service based company. Please tell me advantages and disadvantages. Thanks -Mahantesh
  3. M

    Written test paper of ARM

    Hello friends, Can any one send me the format of written test paper of ARM. Thanks in Advance Mahanthesh
  4. M

    Why violations do you try to fix when you have limited time: setup or hold?

    Re: Timing closure doubt Hi, I have one interview common question in timing closure. The question goes as follows. Suppose there are 10 setup and 10 hold violations in a design. Manager will come and tell you that design needs to be taped out tomorrow. As much as possible violations need to...
  5. M

    Crosstalk b/w two different metal layers

    Thanks Albred, Metal 2 & 3 will be perpendicular to each other. Suppose in metal 2 & metal 4 there can be crosstalk right? I also wanted to know the whether crosstalk is more between same metal layers or in different metal layers with spacing is same for different cases.
  6. M

    Magma & unix (unix cmds in magma)

    What command u want to run? Just type the command it will work.
  7. M

    Why violations do you try to fix when you have limited time: setup or hold?

    Hi, I have one interview common question in timing closure. The question goes as follows. Suppose there are 10 setup and 10 hold violations in a design. Manager will come and tell you that design needs to be taped out tomorrow. As much as possible violations need to be fixed. How you go about...
  8. M

    Crosstalk b/w two different metal layers

    crosstalk between metal layers Hi, Crosstalk between two nets, is it possible to happen between two different metal layers of signal routing i.e metal 2 & metal 3? Thanks in advance Mahanthesh
  9. M

    How is .lib converted to .db?

    Re: .lib Thanks ravurig
  10. M

    about multi-voltage technique's application

    Hello k_vlsi, I think multiple vdd is possible between two FF's. This can happen when two FF's are placed in two different subchips and path exists between those FF's. In this explanation i am assuming that subchips uses different vdd. Thanks & Regards Mahanthesh
  11. M

    How is .lib converted to .db?

    Hi, How is .lib converted to .db? Thanks in advance Mahanthesh
  12. M

    Question on Digital design

    Hi shantha, Have u taken care that sum of the delays of the two inverter should be 1/4 the time period of the clk ur applying at the input of combi circuit. The combi ckt as it looks should work. I wanted to know what is the output ur getting? Regards Mahanthesh
  13. M

    about multi-voltage technique's application

    Hello eagle, Usually different voltage domains are used for different subchips in the design. A path running from one subchip to other subchip will be their. So there can be multi- vdd combinational logic circuits in the timing paths running from one subchip to other subchip. Regars Mahanthesh
  14. M

    BIST controller for ram and rom

    U can look into this book **broken link removed** by vishwani agrawal or Digital Systems Testing and Testable Design Miron Abramovici, Melvin A. Breuer, Arthur D. Friedman http://as.wiley.com/WileyCDA/WileyTitle/productCd-0780310624.html I think this is sufficient......
  15. M

    standard cell characterzation

    Please elaborate the question....
See more

Part and Inventory Search

Back
Top