BIST controller for ram and rom

[leongch]

Hi,
I am currently want to design a BIST controller for ROM and RAM. Can anyone give me some info about it?

1. how could we determine the test pattern into the RAM?
2. how can we determine the fault coverage?
3. If I am newbie, I just want to design the BIST controller for RAM, where should I start from?

Thanks...

 

[mahanthesh]

U can look into this book

**broken link removed**
by vishwani agrawal

or

Digital Systems Testing and Testable Design Miron Abramovici, Melvin A. Breuer,
Arthur D. Friedman

http://as.wiley.com/WileyCDA/WileyTitle/productCd-0780310624.html


I think this is sufficient......

 

[stocking]

Now I am doing the DFT work, I think you should the read the the bist_gd document of ment0r. It is useful that you study the bist design.

 

[mvkarthik]

Normally in the companies there would be certain EDA tools for generating the logic that can test these memories. E.g Mentor / LogicVision.

Typically the BIST controllers that are going to be generated will have test algorithms built into them. ( E.g Marching 0s , 1's Checker - Board ...). To summarize BIST Logic is going to test your RAM. In the case of ROM depending on the data you store in the ROM, you will have a signature that needs to get verified at the end of the test.

Typically Memory BIST converage is not so easy to calculate. Because it's not so easy as you deal with logic. The kinds of faults that you have in the memory are totally random. Typically depending on the patterns that the algorithm uses, the membist converage is given. This typically comes from the memory PE.

 

[Thinkie]

I think you can find BIST wrappers for memories.... isn't that what you are looking ?