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Why violations do you try to fix when you have limited time: setup or hold?

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mahanthesh

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Hi,

I have one interview common question in timing closure. The question goes as follows.

Suppose there are 10 setup and 10 hold violations in a design. Manager will come and tell you that design needs to be taped out tomorrow. As much as possible violations need to be fixed. How you go about fixing these violations?
Which violation you try to fix either setup or hold and why?

Guys who have the experience of tape out of ASIC designs please help me.

Thanks in Advance
Mahanthesh
 

asic_bh

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Re: Timing closure doubt

setup violations are fixed ny removing delay, hold time by adding delay.
It is easy to fix set up then hold violations.

setup violation can be fixed by piplining the combinatorial path. But this might change the design latency. Try to reduve the logic levels on critical path.
 

rakeshnunna

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Re: Timing closure doubt

Hi Mahantesh,

Hold violations are more critical than set-up.I would fix the hold and then try set-up.Bcoz to avoid set-up problems you can reduce the frequency of the design to make it work.But if a hold problem persists your chip functionally fails

Touching the database when you are having a tapeout tomorrow is the last thing you want to happen to your design. Bcoz the moment you touch your design you need to complete a loop of sign-off timing & phyiscal verification.moreover you need to do lot of post GDS work before tapeout.
 

rajesh9999

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Re: Timing closure doubt

If the tapeout is next day, then only an in place optimization, an ECO should be tried for setup voilations. This means the tool will preserve all the routing and makes minimal changes to the netlist (for example only adds buffers, not logic restructure ..etc). If this fails then the chip could stiil be taped out but should be run at lower frequencies.

Hold times are easier to correct and also critical (because the chip will not work at any frequency if there is a hold voilation), so they should be fixed without question.
 

no_mad

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Timing closure doubt

Hi,

I believe you need to do CTS as well. Therefore, I would definitely fix the setup violation first and then perform CTS.

Next, I will perform setup time analysis again and optimization to check any violations. Fix the hold time after CTS is more accurate because now all the wire network have real delay.

Previously, we only use Wire Load Model for net delay calculation. This is not accurate.
 

mahanthesh

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Re: Timing closure doubt

Hi,

I have one interview common question in timing closure. The question goes as follows.

Suppose there are 10 setup and 10 hold violations in a design. Manager will come and tell you that design needs to be taped out tomorrow. As much as possible violations need to be fixed. How you go about fixing these violations?
Which violation you try to fix either setup or hold and why?

Guys who have the experience of tape out of ASIC designs please help me.

Thanks in Advance
Mahanthesh


Along with the above question one more constraint......Manager is comitted to deliver the design with the specified freq u cannot reduce the freq for fixing setup violations.
 

flyankh

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Timing closure doubt

Hi
I will fix hold violation first.because it is easy to fix.And I think the setup violation is easy to fix on frontend but difficult to backend.So let the setup violation be there if the design is not small.
Above all ,setup violation makes us to decrease the freq,but hold violation can make the chip failed


flyankh
 

rameshsuthapalli

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Timing closure doubt

Hi mahanthesh,

u have to ask some question to the manager.1)wether the design is already P&R or it is before P&R.
pre P&R:-
1) u have to fix the setup than the hold bcz if u fix setup the clock skew after P&R the hold will be fixed and there may be a chance of the some setup will be fixed and some more will come newly.
The hold will be fixed by using the delay cells or the buffers cells. at the P&R stage .
post P&R:-
1) u have to fix the Hold than the setup if hold is there the chip will not work . if setup is there the chip will work with the redused frequency.so u have to fix the HOLD first.
2) the hold violation will be fixed by inserting the delay cells or the basic buffers in the violating path.
]3)After fixing the HOLD u have to goto find the which path is going to cause more violation in the setup. ADD some buffer or ad just some drivestrength of the more delay cell and finally do the STA for the vilating report. i think this will remove all the above problems if itis not removing all. do the step 3 for the violating path till the all possible violations are removed.

regards
Ramesh.S
 

pratap_v

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Re: Timing closure doubt

hi
i would go for fixing the hold violations, because the setup violation even though not fixed, can use the design for the lower frequencies. Since the hold is independent of frequency has to be fixed early.
 

yln2k2

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Re: Timing closure doubt

Hi ,

Tapeout database should be not have holdviolations , In silicon u can' fix the same where as setup violations can be avoided by reducing chip frequency ...


regards
yln
 

sameer_dlh25

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Re: Timing closure doubt

Hi mahanthesh,

As everybody emphasized I also agree that you need to fix the hold first and then setup. Without fixing the hold design is defiantly not going to work.

One more thing is if your setup violations are small enough so that you can overcome these by changing the drive strength the it is OK. Otherwise fixing the setup is much more difficult then hold fixing which is usually a buffer insertion in the data path. In brief setup fixing (if violation is more then 10% of clock period ) is time consuming process and you may slip the deadline.:cry:
 

Thinkie

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Timing closure doubt

Definately hold first. The hold violations your device may not work at all. With setup violations it won't work under worst case conditions.

Inserting buffers to fix hold with an ECO it quick and depending on the size of your device it can be done in a day. Maybe the PnR guy can add manually the delay by inserting gates.

Fixing setup violations is a lot more complicated and may require ReSynthesis and a totally new PnR which may take a week
 

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