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input clk, rst;
input [255:0] din; //input data；
input vld_in； //input data valid flag；
input sop_in; //input data packet start flag
input eop_in; //input data packet end flag
input [4:0] num_in; //the valid byte number of input data；such as 1：din[255:248] is valid...
From Google:
Post Silicon Validation, is basically a validation method to make sure that your fabricated chip (since it is fabricated it is post silicon) is working correctly. Basically it is including all testing methods (testing silicon on board in the labs).
It is done to find out if the...
I want to test a fifo. the fifo read interface have three signals "rd, rdata, nempty".
I hope when nempty is valid, the testbench will assert rd to begin a read operaion.
But in SV program structure, the rd sigal always delay one cycle, maybe because clocking structure.
Can anyone give me one...
Hi,
Don't be hesitated, learning vhdl programming and fpga design is not hard. You just need a good book and some practice.
There are many books for vhdl learning, you could google it.
"http://www.asic-world.com/vhdl/index.html", this site is also a good beginning.
Enjoy study.
I like to know how multi-core CPU implements the instruction "read and swap".
Is there a reg which store the memory address that is accessing by cpu? then any other cores that want to access this memory address will be blocked.
Does anyone confirm my idea?
Or give me some links or books to...
Dose anyone know how fast CRC coding could be generated and checked now? 5Gbps, 10Gbps or 50Gbps?
Is there any new generation method for high-speed data?
In my method, I have to do 250bits computation at 200MHz system clock for 50Gbps interface. It is hard for my FPGA.
could anyone give some...
Re: STA doubt
Hi,
If you do not set this path as multi-cycle, and your combo-cloud delay is bigger than one clock cycle, your sta tool will warn this violation in report!
There are many pdf on this site you could refer to.
some site is useful:
www.opencores.org/ : useful design exaple.
www.soccentral.com/ : some tutorial and paper.
a false path is use to tell STA tools not to analyze this path.
this path is your design's feature, such as reset path, ATPGEN path.
these path can not be removed from your design, because it is useful to your design. you must keep them.
If you find some false path is not useful, maybe you can...
Re: PLI vs DPI
As I know, PLI is the programming language Interface for Verilog;
It is used to connecting C language with Verilog and use C functions in Verilog;
I have no idea about DPI. Sorry!
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