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on the above i missed the topic called retention cell.The concept of retention cells is to save and restore the (instead of supplying x values )data values prior to cascaded partially power shut off block.let us assume a lamp which works with solar energy during day time its power is shut...
they will float(unaware the value is 0 or 1)
To eradicate such an issues isolation blocks are used after output of ON_OFF blocks(power off modules) .
which it wont give a floated values to the inputs of the other blocks or dependent blocks
this is done in two sections @ rtl level power...
try like this
very first in verilog itself write a test bench.
use a concept called driver which it inter relates tb and your dut
in that driver concept you write all the routing connections
if you are good in writing tasks and functions write them in driver.
now write an another module ...
hai i am new in power intent verification seeking help
hai i am new in power intent verification
now i am reading specs of upf and cpfs can able to write cpfs and upfs but no idea about tools what tool to use and what will be the output report of the power intent formats.could you help me out...
Hi pals,
i am new to low power intent verification field,i am dealing with cadence(CPF) common powr format
i am a beginner in that .
can any one suggest the related docs and examples for that.....
i learned (UPF) unified power format but i dont know what is the output of that file...
Hi palz,
***********comment on my thesis regarding upf and cpfs***********
In my thought of writing upf/cpf commands is like (just imagine) genertating power supply to a town
the main design is like town
set_scope town
each sub_domain is like a house,hospital,factory etc
create_power_domain...
In my thought of writing upf/cpf commands is like (just imagine) genertating power supply to a town
the main design is like town
set_scope town :inupf
each sub_domain is like a house,hospital,factory etc
create_power_domain hospital -domain {hospital} :in upf
creating power supply ports is...
Hi evesjh77,
i want to functionally verify the low power design using cpf files
i have a lot of questions regarding cpf
can u please share your information about cpf elobarately.
like what tool is used to compile it.
what is the output file format it comes out after...
well i have a practical answer for differentiate blocking and non-blocking
suppose if u see a running race we have some types
relay running race and normal race
in normal race all start in a same time.
simply i define it as non-blocking statements which start executing in 0time...
hai
this is sai...
what we call if a gate output is given feedback to input ,combo are sequential?
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