why negative supplies not used in designs?

[nitint08]

Now designs use +ve supplies either in normal design or be it a LP design, ground supply remains 0.0 while power supply
varies from 0.8 onwards.
But earlier designs use both -ve and +ve supplies? Increasing design complexity and implementation(i.e. handling -ve and +ve supplies ckts.) are the reasons which guided the designers to opt for +ve(single) supplies which is also adopted by the industry(i.e. in available power formats also, there is no way to define -ve supplies and design's power-intent can only be difined using +ve supplies).

Since the supplies absolute potential is become narrow(0.0 - 1.2), having use of -ve supplies may increase scope having multiple power-domains under specific top potential.

 

[cks3976]

Nitin, your understanding is not correct. Negative supplies are still being used. Most telecom designs still use negative supply. For example Texas instruments produce PTN78060AAH (Plug-in Power Module - Non-Isolated POL - PTN78060A - TI.com), which is used for powering the ADSL analog front-end devices that use negative supply.

And isolated powers denote negative supplies too..

Op-amps will use a negative supply and so on..

 

[nitint08]

Ok. Since i didn't see designs having -ve supplies now so took the assumption that due to implication complexities such approach is not being adopted.
Thanks for correction.

But when i'm trying to define power-intent of design having -ve supplies than this is not possible.
For example, power-intent of design having -ve supplies cann't be defined both in upf and cpf. Is it possible to define power-domains having -ve and +ve supplies?

Also the Op-amps and ADC are purely analog where -ve supplies being used while power-intent is only meant for digital designs and for this reason -ve supplies are not supported in latest power-formats in the industry(UPF/CPF/SGDC). Is this correct?

 

[logiclife]

hai i am new in power intent verification seeking help

hai i am new in power intent verification
now i am reading specs of upf and cpfs can able to write cpfs and upfs but no idea about tools what tool to use and what will be the output report of the power intent formats.could you help me out


seeking help

 

[nitint08]

With Power Intent, one can specify or define the designs power need(i.e. how many type of power islands are there, at which voltage they are operating, when they will be turned off/on, what kind of techniques needed when they are turned off, what kind of cells to be used between power islands).
All this information + more is specified with help of two standard format CPF and UPF. CPF from Cadence, UPF earlier from Synopsys but not IEEE standard. Both release newer versions time to time which impicitly means that Tools which work on these power-intents should support the latest versions which includes more features and better process of defining power-intent.
Currently CPF and UPF have released 2.0 versions. There are new changes in the latest verions which can be figured out with there LRMs.
Earlier also lowpower Designs were developed and verification was also used to happen but newer approaches CPF/UPF + new tools makes the power-verification more focussed and track or raise all the different case secnario that may damage the design at the end.
Power-intent verification can be started at RTL level when only functional design is available which can
continue after synthesis (when gate-level netlist) is available and can
still continue till post-layout netlist (i.e. at pg-netlist when lib cells get connected to the relevant supplies).

Since the design complexity has gone to multiple folds so tools are needed which read the power-intent and design, and tell the missing holes in the design which without the tools is not feasible now.