Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Power consumption in IO can be calculated in the same way as in core.
P = P_dyn + P_lek ;
Dynamic power is related to Pad capacitance and signal switching rate.
Leakage is process relevant.
Hope it helps.
constrain on pad?
But Pads will introduce additional delay into timing paths, if you only synthesis the core, please add more margins on input and output delay.
Gate simulation is very important and can't be replaced by PT/FM.
Only if you can ensure your synthesis and STA scripts are correct. But this seldom happens.
128 QAM Demodulator
128 QAM is quite different with 16 QAM.
It is more complicated and I think though 16 QAM is a good start point, their implementations will be very different.
At least the equalizer is more complicated.
There is a good verification software pprovided by Sysnopsys called Telecomm workbench. It is a system-C package. It runs fast and has a lot of good features supporting Telecomm simulation.
I guess you're looking for MPEG or H.264 encoder/decoder RTL code. There're no high quality code for this. And there is license to prevent publishing such kind of code.
question about soc
In general, good SDR DDR or DDR2 chips will handle ECC and error correction automatically. Vendor will guarantee the quality of these SDRAMs. We need not to concern about this.
I recommend to use as more as ripple stages to implement the counter in case of the TIMING is not violated.
If your design is runnung at a very low frequency, try more stages. If a higher frequency is needed (e.g. 200MHz), a single stage must be used.
After CTS, main clock needs to travel through a lot of clock buffers to reach the register's clock. Though no timing information is included, simulator recognize this as several delta delays. How many levels of clock buffer will cause how many delta delays. So there'll be timing violation if...
I recommend use DC to resynthesis the whole design. Only in this way you can get more optimized circuit. What you need to do is only convert ROM, RAM and other analog IP to corresponding ASIC IPs.
I think the internal logic decide the bus switching rate. Maybe you can try cache data in register, fetch data from cache when needed, not from outside through bus.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
