Constrain on pad or on core when using DC or PT

[jjww110]

when using dc or pt ,we should set constrain on pad or on core(without pad),which method is better?

 

[silencer3]

Re: constrain on pad?

Apply all constraints on the core and synthesize it without IO pads. After synthesis insert IO pads into the netlist using scripts or manually. But if u r inserting PADs into RTL before synthesis, then put a dont touch on all IO pads, and do synthesis.

better to follow bottom-up compile stratagy to acheive better performance. use incremental compile as well.

 

[power-twq]

Re: constrain on pad?

We set constraints on core, then we hand instantiate PAD,

lastly we through simulation to find and fix PAD related timing problem.


best regards

when using dc or pt ,we should set constrain on pad or on core(without pad),which method is better?

 

[soccer]

constrain on pad?

Apply all constraints on the core and synthesize it without IO pads. After synthesis insert IO pads into the netlist using scripts or manually. But if u r inserting PADs into RTL before synthesis, then put a dont touch on all IO pads, and do synthesis.

 

[lijian_18]

constrain on pad?

But Pads will introduce additional delay into timing paths, if you only synthesis the core, please add more margins on input and output delay.

 

[AH Ling]

Re: constrain on pad?

You must choose the right IO PAD that has the right/suitable intrinsic timing delay...else you will have to constrain your core design at very high clock frequency to achieve your specification. THough you will be able to achieve your spec, the layout engineer will face difficulties if you have to synthesize your core at 10 times of your spec.

 

[rakeshnunna]

Re: constrain on pad?

Its better to constrain without the core without pad only.

Added after 1 minutes:



Sorry I mean to say, it is better to constraint the core without the pad.

 

[luancao]

Re: constrain on pad?

DC is used for systhesis while PT is used for timing analysis.

For timing analysis, of course, you should get it done on whole chip level. IO is one of the most important part and often is the critical path.

For synthesis IO is treat as a macro. You could decide according to your design flow. I often get it just connected and linked by DC.

May it be help.

 

[Thomson]

Re: constrain on pad?

Is there some basic rules regulating the writting of the I/O scripts since the context of the chip, before the integration, is not very clear?