Is PT/Formality is replacement of Gate Sim

[spauls]

Hello All,
I have one doubt,
Suppose your Timings are met in Prime time and design is passes in Formality ,
Then it is OK to do Gate Sims.
Please advice.

 

[sunms]

Of course it's OK to do post_sim.
In our company, only STA and Fv is passed,then we will do post_sim. And we will not spend too much in post_sim. But at present,post_sim is still a must process.

 

[tony_taoyh]

Yes, I also think post sim is very important,
because it can check whether the timing script is in mistake..
1) Pre layout (unit delay) is also important;
because sometimes, the formality can miss
some mismatch; I have meet this case for one time.

2) Post layout is to check whether the timing constraint s is put correctly.

So, also necessary...

What I think, do not rely on one tool...
The EDA vendor always say their tool is perect..
But when the problem generate, just hmmmmm....
Maybe after short time, one new version is there,
welcome to download...

 

[AlexWan]

hi, spauls

Formal and STA can't replace the gate simulation(pre-simulation and post-simulation).

1). Formal tools only check the function of the design. It compare design between the different levels, and don't care the timing.

2). STA tools will check the timing of path which we don't set "flase_path" on. Now in SOC design, there are many clock domains. STA normally can't check the path through different clock domains.

So we have to do dynamic simulation, gate simulation.

Good Luck

 

[ic_kuang]

Now, we do not have simple way to check whether the sta constraints is correct. Post simulation is a safe method.

 

[funzero]

Gate-level Simulation is a must do .
some faults must be simulated to find.
Function correcty must be verified at gate-level just like at-speed test!

 

[power-twq]

no, perhaps you should run a simple gate-sim to verify IO timing is ok!!

Hello All,
I have one doubt,
Suppose your Timings are met in Prime time and design is passes in Formality ,
Then it is OK to do Gate Sims.
Please advice.

 

[lijian_18]

Gate simulation is very important and can't be replaced by PT/FM.

Only if you can ensure your synthesis and STA scripts are correct. But this seldom happens.

 

[jjww110]

for the safe,please run post-sim

 

[JesseKing]

If the design have only one clk, i think post-sim can be replaced by STA/FV.

am I right?

 

[odeafeiner]

If the design have only one clk, i think post-sim can be replaced by STA/FV.

am I right?

No. I don't think the post-sim can be totally replaced by STA/FV even with only one clock.