tavidu
Member level 1
question about soc
the code of cpu core is stored at DRAM.
but as we know, DRAM has soft error(SE).
When SE occured, the chip will die.
So We can use ECC to correct 1 bit soft error of DRAM.
my question is :
Among SDR, DDR, DDR2, which one is more stable for code storage according to your SOC design experience.
the code of cpu core is stored at DRAM.
but as we know, DRAM has soft error(SE).
When SE occured, the chip will die.
So We can use ECC to correct 1 bit soft error of DRAM.
my question is :
Among SDR, DDR, DDR2, which one is more stable for code storage according to your SOC design experience.