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@betwixt
actually the lower 3 bits of i are directly routed to the lower 3 bits of the answer hence you get 10100 from the 5 bit subtractor and 010 from the input i and concatinating it yields 10100010 which is 162. subtracting 8 is the actual answer but why use a full 8 bit subtractor when...
converting 8 to binary we get 1000. this means the lower 3 bits of the answer is going to be the lower 3 bits of i,no matter what. So you can instead use a 5 bit subtractor that does(i>>3) - 1 which is going to be a lot simpler and saves area, power and has higher speed. Whould this be a good...
Hi,
I am trying to simulate UVM methodology using rivera pro. I can compile the program using commandline alog -l uvm filename.sv . but I do not know how to add the uvm libraries to the GUI simulator. when i try to compile using HDE>simulate I get errors saying that the library is not found and...
hey guys. I am trying to simulate a processor on vhdl and here's my problem. I am having trouble when updating my PC. the sequential code for updating PC is given below
As you can see I am trying to check for a data hazard stall and if it happens, the my PC_reg shouldnt update. but as seen...
gpdk045.....i am a grad student:). so u saying the cadence online support has info on standard cells? i am lookin for info on what is oai22x1, what are the list of std cells u can have, naming convention etc..
Could anyone give me some info on standard cells in cadence? I would like to know the list of standard cells, then naming conventions etc? like when cadence converts the verilog module into a schematic entry, it picks the various modules based on the name right? where can i find all such info?
So I have a DRAM cell simulated. I understand we are not to raise the word line when the column line is low since there is no need for that. But shouldn't the capacitor be discharging when the gate voltage is low? why is it at about 750mV when the gate voltage is low and the source is high?
so I add a new layout for the device like u said in the GPDK library and give it a name like trenchmimcap......now i would have to make it get detected as a device model right how do i go about doing that... and I need to have a higher capacitance for the model. I assume i do that in the...
So I got a reply from cadence forum that I should be doing the following to introduce my own device.
you would need to introduce some different layer to indicate that this is different. You'd then need to modify the pcell to alter how the layout is drawn, alter the simulation models to reflect...
Width and length are dependent on the process you are using. for a 45nm technology, the minimum length you can have is 45nm. You can also customize the width and length for tuning the digital circuit. for example, if you want equal rise,fall times, you size the nmos and pmos in the ratio of 1:3.
Hi
I am using GPDK45nm technology for my design. I am thinking of simulating a DRAM memory cell. But problem is i cannot find deep trench capacitors that gives about 30-50f F to store the charge. I am onl able to use the default mimcap which needs a very large area for the required cap. could...
https://www.emrl.de/imagesArticles/DRAM_Emulation_Fig2.jpg
I was studying about DRAMs and was wondering whether the DDR2 ram and other types of DRAM still use the same cell design as the memory element(a transistor with a capacitor) or have DRAMs advanced beyond the primitive design. I have...
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