# problem when checking signal on rising edge

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#### legendkiller

##### Junior Member level 1
hey guys. I am trying to simulate a processor on vhdl and here's my problem. I am having trouble when updating my PC. the sequential code for updating PC is given below

As you can see I am trying to check for a data hazard stall and if it happens, the my PC_reg shouldnt update. but as seen below, the PC updates on the next rising fall edge. I presume that this is because of setup hold time violations. The stall signal is not rising up early enough to be detected. but due to my design I am able to generate a stall signal only at that instant. So when i want the PC to stall in address 13, it actually stalls in address 14. I am out of ideas on how to go about here. any help would be appreciated.

a little info on the stall signal. a forwarding unit checks for the register address(which are updated on the rising edge) in the pipeline and generates the stall signal. the forwarding unit itself is combinational. i doubt that it would help me if i make the forwarding unit sequential on the rising edge.

Code:
process(clk,rst)
begin
if(rising_edge(clk)) then
if	(rst = '1') then
PC_reg <= (others => '0');
elsif(branch_equal = '1') then
elsif(data_hazard_stall = '1') then
PC_reg <= PC_reg;
else
PC_reg <=	 STD_LOGIC_VECTOR(unsigned(PC_reg) + 1);
end if;
end if;
end process;
end Behavioral;

#### sharath666

On comparing the code with the waveform, I find that the behaviour is as expected.
1. You must understand that when a signal goes high, this high value is checked at the next rising edge of clock. So stall goes high at 1 rising edge, this 1 will be checked at the next rising edge.
2. So if you want PC_reg to stall at 13, you must generate stall 1 cycle earlier.
3. There is no question of setup-hold violations as this is pure RTL simulations.

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