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Conformal LEC problem

Learner12

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Can anyone help me how to map this DLAT Gated clock issue in Conformal LEC . I am getting only in Revised side.
 

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RC* clock gatings traditionally added by genus during synthesis, the are seen as unmapped/unreachable points since no influence on output. they are not exist in rtl , just added by synthesis tool. so it doesn't mattern.
 

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