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I think there is a mismatch between what you are saying and what iam refering( IAM REFERING ALGORITHM IN THE LINK you are refering normal pencil and paper type i guess).
Lets follow the normal decimal divison
for dividend 15 and divisor 10
10)15(1
10
-----
5 (now this...
I did 2's complement after shifting in every step in iteration 1 accum is 0001 (after left shift) and divisor is1010 whose 2's complement is 0110.
0001
+0110
--------
0111
-------
like this i did for every step in post #3 (please see it)
Regards
The first link provided you is exactly same as the link i mentioned except some typo error.Actually i resolved the issue i un commented temp to signed and increased bitwidth of temp by 1,Then it is giving proper results.The problem is overflow of addition of 2's complement of divisor and temp...
Thanks for your suggestion ,here i did manual performed algorithm described in that link and simulated the code for that values they are matching but not equal to pen and paper type division.see the figure and algorithm flow for 15/10
accum mq
0000...
Hi,
I have found restoring division algorithm in below pdf.**broken link removed**
i used 4 bits for dividend ,divisor,quotient, what i observed is for 15/10,the algorithm is giving quotient as 14 and reminder as 3 but actually it should be 1 and 5 respectively.Is there any bit length problem...
actually i observed synthesis schematic which shows that cntr is actually mapping to clock enable pin of flipflops(0 to 3) and ff_2 (FDRE).Should i declare multi cycle constraints on CE pin or data pin of flip flops? which is correct here i am attaching constraints files.
set_property...
a) what i understood from that paragraph is (assume same clock domain)if we sample the signal at known time we should declare it as a multi cycle path.suppose if i sample the signal for every four clock cycles we should declare setup and hold multiplier in multicycle path as 4 and 3 for start...
That means every multi cycle registers is not needed to constrain as a multicycle path? or we need to put a multi cycle if and only if there is a combinational delay more than one clock cycle? which one is correct?
**broken link removed**
In above link page no 289 last paragraph states that...
Hi,
i have seen example code for multi cycle path in below link.
https://www.edaboard.com/threads/333626/
i am trying to understand multi cycle path implementation using above code in vivado.
module mc_test(
input wire board_clk,
input wire rst,
output reg [3:0] ff_1...
Hi,
I need help regarding fixed point arithmetic operations,
There are two numbers one is of 24 bits in this 1 bit for sign and 13 bits for integer and 10 bits for fractional part.The second number is 16 bits in which 1 bit for sign and 15 bits for fractional part.
when i multiply both numbers...
Hi,
I have doubt on non back-to -back write command,in page no 92 diagram it is specified that maximum allowed delay from address to command is two clock cycles,in the third case app_wdf_wr_en is asserted after(two clock cycles) de-asserting command signal,still it has shown that new data is...
i used the following code in my test bench
$sformat(index, "%0d", i);
filename = {"file",index,".txt"};
$readmemb("filename",mem_in_R);
simulator is giving warning as .txt file can not be found to for readmemb function.
here the mem_in_R is an array to store the 8 bit binary values of depth...
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