fixed point arithmetic in verilog

[kommu4946]

Hi,

I need help regarding fixed point arithmetic operations,
There are two numbers one is of 24 bits in this 1 bit for sign and 13 bits for integer and 10 bits for fractional part.The second number is 16 bits in which 1 bit for sign and 15 bits for fractional part.
when i multiply both numbers i will get 39 bits (N1 + N2-1) then i have to add four multiplied values .

In which msb bit for sign and 13 bits are integer and 25 bits are fraction.(1,13,25)
i want to add four such numbers (1,13,25) numbers and convert back the result to (1,13,10) format.
Then the result bit width is of (1,15,27) to avoid overflow . On paper to get the result back to (1,13,10) iam taking MSB 10 bits of 27 for fraction and MSB 13 bits of 15 for integer .

But when it comes to implementation it is just addition of four 39 bits which need 41 bits .
In this 41 bits how i have to separate sign integer, and fraction.? r should i use bit width as 43 bits?

Regards

 

[vGoodtimes]

you would need to get the 13 lsb of the integer part. There can be overflow as a result. This would be the same if there were no fractional part. To avoid that, you could have 15 integer bits and 8 fractional bits.

 

[bravoegg]

for general cases, multiplying Q14.10 * Q1.15 would result a Q15.25 , say if you do a 111 * 111, you'd be needing 6 bit to represent the result, instead of 5.

then after addition of four, the Q15.25 turns into Q17.25. Overflow and loss of precision are both involved because now there're shorter integer part and fraction part. My suggestion is contain all the integer part and sacrifice more fraction part, say you get a Q17.7, still 14bits but with different Q-format.

It might be the cases that the integer parts are more than needed and thus some upper bits of the 17 integer bits could be ignored. But to be certain it's better to simulate them thoroughly beforehand in Matlab.

Sy.