Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I want to design an inductor meter. How to go ahead. I thought to use tuning circuit, where c will be predetermined capacitor and L is unknown(of course). Then, the output of tuned LC circuit will be a sine wave, which I will pass it to comparator (op amp as a comparator)as one input. The other...
I have this Intex 600VA UPS for My PC. The battery has been drained out so totally zero back up. I am basically using this UPS to nullify voltage fluctuations. However from last two days whenever i on this UPS it is making ridiculous noise, very high.I dont know what is the problem.Can anyone...
net27 is not right side of inductor.It is drain of Pass transistor.And net027 is left side of inductor. Should i see output at right side of inductor? :shock:
I am not getting whats the use of ESR capcitor.i know it nullifies one of the poles. But in the figure below.Even without that.The LDOwould be stable right.(Sufficient phase margin)
.
- - - Updated - - -
Another thing. Acc to textbook. Phase margin is calculated relative to -180 degree where...
Hello all i want to find out gain and phase margin of an LDO.So in order to that i have done ac analysis by breaking the loop and placing inductor and Coupling ac to the + terminal as shown here. Is this the right way is my first question
second question.Where the phase angle should start -180...
Hello all. After studying Analog VLSI for a while.Dealing with only low voltages and LDO s. I got to study switch mode power supply under our professor. Being fascinated by the idea of SMPS. I wanted to design a boost converter. I want to double my input voltage. SO used D=1-vi/v0. So i kept...
ya thanks i went through some.But how to perform ac analysis of LDO. I mean Bode plot.To find gain and phase margin. In CADENCE . IT would be very helpful if i get to knw the procedure.
Hey erikl i have designed the LDO for those conditions.LDO pass element has W/L=9m/1u. what about stability of this LDO. what all need to be considered. Does that capacitor with ESR will make sure about stability all the time? By nullifying one pole?
Hello https://www.edaboard.com/threads/292162/#post1249981 follow that thread. And yea the value of W will be in milli not micro. W/L ll be typically w/L=500 + for it to be in saturation and it supports maximum current of yours. For lower current(higher loads) it may slip to subthreshold...
Hi i completed B.E(EC). I have also done UG diploma in Analog VLSI . I am looking for internship in VLSI. It's very tough to find a job by Just B.E level.So thought to do Internship. Please suggest me as how to proceed next? . Under UG Diploma course , I studied About feedback theory,RLC...
Oh thanks for clarifying. I think i should check vds of the pass transistor and vdsat.I think it will satisfy the condition Vds>vdsat(Because i'm getting output voltage as 1.8v).. And yeah i kept W/L very high only considering Ilmax=50 mA. So for all other loads Il<Ilmax.So it shows subthreshold...
should i change W/L of PMOS Pass transistor. Since i ve kept 6m/180n. how about changing voltage at differential pair output?. Since controlling action is done. It will always change . But its voltage should be always less such that Vgs>Vt. Vt=0.4928v. How to achieve
I have done LDO design. Input voltage is 2-2.4 V
Output voltage=1.8v.
maximum load current=50mA
I m getting this output voltage but Pmos pass transistor is going to sub threshold region. Vref=1.16v.
what should be the output of differential pair(Single ended output).what should be done to...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
