Doubts regarding AC analysis of LDO.

[kishore680]

Hello all i want to find out gain and phase margin of an LDO.So in order to that i have done ac analysis by breaking the loop and placing inductor and Coupling ac to the + terminal as shown here . Is this the right way is my first question

second question.Where the phase angle should start -180 or 180. Cause i plotted from 1 hz to 1Ghz and 100 hz to 1G hz in cadence. I got two different results as shown below.

why is that so? . Which is correct and why? ac magnitude=1mv

 

[LvW]

Hello all i want to find out gain and phase margin of an LDO.So in order to that i have done ac analysis by breaking the loop and placing inductor and Coupling ac to the + terminal as shown hereView attachment 93685. Is this the right way is my first question

Yes - for my opinion, it looks good.

second question.Where the phase angle should start -180 or 180. Cause i plotted from 1 hz to 1Ghz and 100 hz to 1G hz in cadence. I got two different results as shown below.
View attachment 93686View attachment 93687
why is that so? . Which is correct and why? ac magnitude=1mv

It does not matter : -180 deg is the same as +180deg.
The critical point is either at -360deg or 0 deg, respectively.
However, I recommend to use an ac voltage of 1V. In this case, the output voltage is identical to the loop gain in dB.
(You know - the small signal analysis is a linear analysis without any voltage limitation due to non-linearities)

 

[FvM]

I wonder what is net27? I guess, it's not the right side of the inductor because it would show a different (wrong) gain at low frequencies.

The loop gain phase margin is probably too low.

 

[kishore680]

I am not getting whats the use of ESR capcitor.i know it nullifies one of the poles. But in the figure below.Even without that.The LDOwould be stable right.(Sufficient phase margin)
.

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Another thing. Acc to textbook. Phase margin is calculated relative to -180 degree where phase starts from 0 degree in that context.but here it starts from 180 deg.Should i have to calculate wrt 0 degree or -180 ? :???:

 

[LvW]

Another thing. Acc to textbook. Phase margin is calculated relative to -180 degree where phase starts from 0 degree in that context.but here it starts from 180 deg.Should i have to calculate wrt 0 degree or -180 ? :???:

When you simulate the real loop gain - that means: including the necessary phase reversal - the phase must start at -180 deg. Otherwise, you would have no negative dc feedback and no stable operating point.
But, what about FvM`s question? Where is your output node?

 

[iVenky]

Hi Kishore. I saw your circuit. But it looks like you don't have a open loop Aβ for plotting the AC response. I understand that by using those capacitors and inductors you are making an open loop but I think it would be much more better if you just short that instead of having a capacitor and open the inductor instead of having it. Anyway I just glanced at your circuit. Also regarding that -180 and +180 deg, it depends on where you see the output. If you have done it correctly then it should be -180 deg so that you get negative feedback. Also could you tell me what those net27 and net027 are? One seems to be okay except that +180 deg but the other one seems to be messy. May be those inductors and capacitors are causing some problems. So better take those off.

 

[kishore680]

net27 is not right side of inductor.It is drain of Pass transistor.And net027 is left side of inductor. Should i see output at right side of inductor? :shock:

 

[FvM]

Hi Kishore. I saw your circuit. But it looks like you don't have a open loop Aβ for plotting the AC response. I understand that by using those capacitors and inductors you are making an open loop but I think it would be much more better if you just short that instead of having a capacitor and open the inductor instead of having it. Anyway I just glanced at your circuit. Also regarding that -180 and +180 deg, it depends on where you see the output. If you have done it correctly then it should be -180 deg so that you get negative feedback. Also could you tell me what those net27 and net027 are? One seems to be okay except that +180 deg but the other one seems to be messy. May be those inductors and capacitors are causing some problems. So better take those off.

It looks like you're not familiar with common methods of biasing a circuit for loop gain simulation. Operating the circuit with open DC loop isn't a solution because it most likely results in a wrong bias point. There are some alternative methods, but the "huge" LC lowpass method is simple and straightforward. You need to check however for suitable LC values and possible side effects. In the present case, the 1 H inductor isn't effective below about 10 kHz and should be changed to e.g. 10e6H. As a result, the loop output voltage as measured at the voltage divider/right side of the inductor is wrong below 10 kHz.

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Should i see output at right side of inductor?

Yes, otherwise your not measuring loop gain. But pay attention to the inductor value. It must be high enough not to load the voltage divider in the frequency range of interest.

 

[kishore680]

Yea sure.Will increase the L value used in the circuit. Those resistive network will not contribute phase. So phase plot remains same i guess.

 

[FvM]

Those resistive network will not contribute phase. So phase plot remains same i guess.

Basically yes, with two reservations:
- L must be large enough in the simulation circuit
- M2 input capacitance will form an additional pole with the divider output impedance in normal operation. You need to assure that it's far above the loop bandwidth. Or add an equivalent series resistor at M2 gate terminal in simulation.

 

[iVenky]

It looks like you're not familiar with common methods of biasing a circuit for loop gain simulation. Operating the circuit with open DC loop isn't a solution because it most likely results in a wrong bias point. There are some alternative methods, but the "huge" LC lowpass method is simple and straightforward. You need to check however for suitable LC values and possible side effects. In the present case, the 1 H inductor isn't effective below about 10 kHz and should be changed to e.g. 10e6H. As a result, the loop output voltage as measured at the voltage divider/right side of the inductor is wrong below 10 kHz.

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Yes, otherwise your not measuring loop gain. But pay attention to the inductor value. It must be high enough not to load the voltage divider in the frequency range of interest.

Hi FvM. What I meant was this- You can give the DC bias point in that ac signal source itself. It was implied when I said that. That should sort out that problem that you are talking about. You know the DC bias point from the operating conditions in Cadence. All you need to do is to set that value in the DC box in the ac signal source

 

[FvM]

You can give the DC bias point in that ac signal source itself.

You can't do that easily. You have to adjust the bias voltage in very small steps until you achieve the intended output voltage. For any input voltage, load or internal circuit parameter change, you have to readjust. That's neither simple nor straightforward.

The basic idea is to keep DC feedback to allow self-biasing of the circuit.

 

[LvW]

Yea sure.Will increase the L value used in the circuit. Those resistive network will not contribute phase. So phase plot remains same i guess.

Yes - basically correct. However, don`t forget the correct magnitude response that is needed to determine gain and phase margin!.
You have opened the ac loop using an inductor - thus, it is logical to use both voltages left and right to this inductor for loop gain simulation.

 

[iVenky]

You can't do that easily. You have to adjust the bias voltage in very small steps until you achieve the intended output voltage. For any input voltage, load or internal circuit parameter change, you have to readjust. That's neither simple nor straightforward.

The basic idea is to keep DC feedback to allow self-biasing of the circuit.

Hi FvM. You know the DC bias point already from the dc simulation. So you can just set it right? You already know the bias point when you were analyzing the diff amp alone for finding out its gain (without pass transistor and feedback). In the above case it is the reference voltage. For proper operation of the diff amp the DC feedback should not change the bias. For analyzing the Aβ plot you should cut the loop right? I mean you assume that dc bias won't get affected even after feedback and find out the Aβ plot right? I mean there should be no feedback even at the DC right for analyzing Aβ? Even if the value is not equal to the reference voltage it would be atleast near the reference voltage. We can make that approximation right?

 

[FvM]

Copying the bias point from a DC simulation and skip the initial bias point solution in AC simulation is one of alternative methods I mentioned in post #8. But it involves switching the circuit topology from closed to open loop between DC and AC analysis. And repeating this steps for each set of operating conditions. There might be reasons to use the method in some cases, but I don't see a purpose in the present case.

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I mean there should be no feedback even at the DC right for analyzing Aβ?

I don't get the meaning. Correct bias point is necessary for AC analysis, DC feedback the most simple way to set it. full stop.

 

[iVenky]

Ya I agree. I just suggested that because we can make the approximation that the DC bias point would be equal to the reference value and check the plot as it would not cause that much difference. That would let us know if those blocking capacitors and inductors are causing any problem to the ac plot though it wouldn't in the present case.

 

[iVenky]

Hi kishore. There is something called stb option in Analysis window. That is much easier to find out the open loop gain