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Hi pancho_hideboo:
Thanks a lot! Dose it mean that the feedback signal traces the input signal more rapidly in a DSM with higher OSR, which leads to lower error?
best,
Ken
Dear All,
Could you please tell me what's the relationship between OSR and ELD in continous-time sigma-delta
ADC? And why lower OSR is more sensitive to ELD?
Thanks a lot!
best,
Ken
Dear all,
I encountered a very strange problem.
I used a crystal for a on-chip DCXO, but sometimes the oscillator did not start up after power-on.
At this time, I need to use my fingers to touch the crystal output cap. on the PCB to make the DCXO start to ocsillate.
I totally have no ideal...
Dear all,
I encountered a very strange problem.
I used a crystal for a on-chip DCXO, but sometimes the oscillator did not start up after power-on.
At this time, I need to use my fingers to touch the crystal output cap. on the PCB to make the DCXO start to ocsillate.
I totally have no ideal...
Dear All,
Could you tell me how to calculate the metal width for a connection which has a very large peak current during dynamic but a low dc current during static? Since the document from foundry just provides current limits for dc or RMS.
Do you have any equation or paper about this subject...
Dear all,
I have designed a fully differential telescopic op with fully differential gain-booster. But I don't know how to simulate the stability of it. Could you help me?
Thanks in advance.
B.R.
Ken
10/27/2009
Dear all,
I want to design a LDO with 0.5V output. As I know, the output voltage is derived from the bandgap voltage by res devider. So it is easy to realize a LDO with output > 1.2V. But how to realize a 0.5V LDO? Could you give me some tips or papers about this topic?
Thanks.
B.R.
Ken
Leo,
Thanks a lot for your reply.
But your method looks like that I should define the mismatch by myself. What I want is that after choosing a size of the resistor or a cap, how to get the mismatch value of them by simulation.
B.R.
Ken
Dear All,
Could you please tell me how to get the mismatch of res or caps by simulation?
I am designing a DAC which is composed of res string and cap array, and I can calculate the mismatching of the element according to the formula in the foundry documentation. But I want to run a simulation...
resistor mismatch
Dear all,
Who can tell me how to choose the mismatch value of the res to design the 7bit DAC with 128 res in series?
I know that a larger size makes a smaller mismatch, but I don't kown what mismatch value can meet my spec.
Could you show me some paper about this? Thanks!
B.R.
sc cmfb oa simulation
Hi all,
I have designed a SC CMFB fully differential op. But I can not simulate the open-loop ac characteristics of it?
Could you help me?
Thanks ahead!
Best
Ken
opamp
Hi all,
Could you tell me the reason of why the closed-loop gain has a ripple will cause the LDO unstable? Please see the Fig. which from "Stability in High Speed Linear LDO Regulator".
B.R.
Ken
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