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How to realize a 0.5V output LDO ?

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ken_cn

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Dear all,

I want to design a LDO with 0.5V output. As I know, the output voltage is derived from the bandgap voltage by res devider. So it is easy to realize a LDO with output > 1.2V. But how to realize a 0.5V LDO? Could you give me some tips or papers about this topic?

Thanks.

B.R.
Ken
 

dick_freebird

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Sub-bandgap references exist, but at 0.5V -supply-
you are probably looking at low-VT ("natural"?) MOS
in a delta-VT scheme. If you only have diodes and
high-VT MOS, that'd be a tough one. What is your
minimum in-regulation supply voltage required?

If you have an auxiliary, higher supply (like I/O) you
might run the bandgap and pass device gate drive,
off that and only the output transistor off the low
voltage.
 

tdy

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divide the Vbg by a res ladder
 

erikl

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dick_freebird said:
... low-VT ("natural"?) MOS
Guess you think of native nfets (Vt ≈ 0) ?
Would be highly welcome ;-) for the voltage comparison!

dick_freebird said:
... only the output transistor off the low voltage.
Wouldn't the output transistor better be a pfet running off the in-regulation supply voltage?
 

dick_freebird

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Depends, a 0.5V output and (say) a 0.6V min input supply
only makes for P Vgs=-0.6V, which isn't going to give much
output current. But if he also has (say) a 2.5V I/O rail then
there's plenty of juice for a source follower output.
s in both N and P. Plus depletion mode that we aren't
allowed to use except as caps (though I have).

Hard to get a natural / native / intrinsic FET on a flow
that deposits epi doped in-situ though.
 

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