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Recent content by Kathan Shah

  1. K

    Sizing of single port 6T SRAM

    Do you mean there is no other method except doing smart brute force like sizing? I was thinking of doing some sweep.
  2. K

    Sizing of single port 6T SRAM

    I am designing single ported SRAM with 6T cell. I am using cadence virtuoso.The components would be write circuit, precharge, sense amplifier, 6T cell, address decoders. It has to be 4 banks of 256 bits so muxes would also be required. How do I size each of them? All I know is about sizing 6T...
  3. K

    What is the difference between Front End and Back End in Digital Deisgn??

    I think frontend deals with highlevel description of circuitry using HDL while backend deals with actual physical layout of the system. Correct me if I am wrong.
  4. K

    Removing latches generated from missing assignment in if statement

    I synchronized it and the latching problem was gone! It required a slight change of logic. I was doing a silly mistake. Thank you for the help for making my work synthesizable!:-D
  5. K

    Removing latches generated from missing assignment in if statement

    I tried doing a= a and b=b but still problem was not solved. I dont know what is causing the problem as I have if statement in a case statement.
  6. K

    Removing latches generated from missing assignment in if statement

    Thank you for your suggestion. b=b will cause reading and writing in same clock cycle which will not be possible.
  7. K

    Removing latches generated from missing assignment in if statement

    I have written an if else statement in VHDL, wherein one signal is used in if statement and not in else statement, which has resulted into latch. This should not happen. One way to remove this is assign signal values in both cases, which is not possible for my logic. What I am doing is similar...
  8. K

    writng a testbech for Floating point adder

    Thank you, I obtained real numbers but could not assign it to input as it is of the type std_logic_vector
  9. K

    writng a testbech for Floating point adder

    Sorry, I forgot to mention it was VHDL. Till now I have written a not so useful testbench for FP adder with a for loop, with i starting from 0 to 100 for giving it to operands, but realized that the number needs to be IEEE 754 format. How about importing test vector from a file? But don't...
  10. K

    writng a testbech for Floating point adder

    I am new to test benches. I need to test the FP adder, with operand a and b. Input I give to them is IEEE 754 single precision floating point number, but the problem is I need to test them on a large range on floating point numbers.(probably in for loop) Since test bench need not to be...
  11. K

    HDL Coding design and methodology

    You can learn behavioral type of programming in VHDL, since it easy to describe the behavior than the structure when complexity goes on increasing.
  12. K

    Modifed non restoring method for square root

    You can paste the url I mentioned in your browser to download the pdf, I understood the way it works, but the algorithm is bit difficult for me to translate it to VHDL.Thank you for showing interest.
  13. K

    Modifed non restoring method for square root

    Hi, I found this pdf which shows the algorithm for the square root, but I couldn't understand it properly. Can any one help? I want to write a VHDL code for it. Shifting part in it is confusing. telkomnika.ee.uad.ac.id/n9/files/Vol.8No.1Apr10/8.1.4.10.01.pdf
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