writng a testbech for Floating point adder

[Kathan Shah]

I am new to test benches. I need to test the FP adder, with operand a and b. Input I give to them is IEEE 754 single precision floating point number, but the problem is I need to test them on a large range on floating point numbers.(probably in for loop)

Since test bench need not to be synthesisable I can use float as a type. Can anybody please help me providing with the example or some for declaring and using the float numbers for single precision 32 bit?

Thank you.

 

[TrickyDicky]

What language are we talking about?
And what have you done so far?

 

[Kathan Shah]

What language are we talking about?
And what have you done so far?

Sorry, I forgot to mention it was VHDL. Till now I have written a not so useful testbench for FP adder with a for loop, with i starting from 0 to 100 for giving it to operands, but realized that the number needs to be IEEE 754 format.

How about importing test vector from a file? But don't know how.

 

[TrickyDicky]

using the floating point library thats part of VHDL 2008, you can easily convert real types to IEEE 754 format. If you have an old version of modelsim, you can get a '93 compatible version from www.vhdl.org/fphdl . Newer version of modelsim (10+) are 2008 compliant and already have the library.

You can also read real types from a text file. There are many textio tutorials on the web. You may want to consule google.

 

[Kathan Shah]

Thank you, I obtained real numbers but could not assign it to input as it is of the type std_logic_vector

 

[TrickyDicky]

there is a to_slv function in the floating point library.