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Hi C_mitra,
Thank you for your reply. You explain it very well but I still have some question about your reply
In your example, the linear scaling by a factor of 2 and the corresponding parasitic capacitance shrink by a ratio of 4.
But why does the power consumption decrease by a factor...
Hello all,
I know that the topic seem not suitable for this board due to it is more related to digital circuit.
But I think this topic could be simply as "How does the parasitic capacitance shrinks as process scale down? "
So, Those who good at design Analog circuit design must know(or care)...
To SunnySkyguy
Thanks for your billion explanation.
But please forgive me that my knowledge is limited.
"A counter is a chain of; async ripple counters or sync flip-flops . A PLL phase comparator is only an XOR gate with a VCO, so has fewer gates." <= Does it means PLL based may cousume less...
Hello everyone,
My research topic is related to biomedical field.
The modulation technique including amplitude shift keying(ASK), frequency shift keying(FSK) and binary phase shift keying(BPSK) was normally used in wireless transmission.
Some material told me that only ASK modulation...
Thanks a million, SIDDHARTHA HAZRA
I think you must be a expert in this field
As your said, the output noise of error amplifier and power supply noise should be the same if PMOS based LDO was chosed
I don't quite understand about your description "But in your circuit the error amplifier is...
Hello everyone,
I am new to low drop-out voltage(LDO) regulator design
I have ever read a famous paper which tell me why PSRR get best reslut at low frequecny , 20db/dec degrading as frequency beyond error amplifier(EA) bandwidth, reach at worst case when frequency at the gain bandwidth...
In my case,the coupling coefficient is very low due to the two inductors placed 10cm apart.
I want to connect one terminal of each coil to ground and the other one to VNA port.
And transform the measured S parameter into z matrix.
Mutual inductance=imag(Z(2,1))/(2*pi*freq)
Am I right?
Dear all,
I want to use vector network analyzer(VNA) to measure the coupling coefficient of two wired inductors which operated at low frequecny(1MHz).
I have consult the user manual of VNA and the operation frequency at 1MHz is permissible.
But I don't quie sure that the value is correct in...
Does that mean the nominal resistance is created virtually for calculated the output power.
It didn't exist in real application of class E amplifier.
But if it is true. how to get the power conversion efficiency of this block only in the whole system.
Dear all,
I wanna know how to measure the 13.56MHz class E power amplifier.
This question may sound easy to deal with it but it have confused me for a long time.
I know how to get the optimize value of each parasitic componenet, including parallel capacitor Cp, series resonant circuit...
Sorry, I don't notice your reply immediately.
Thank for your advice. I think that the thing is easier than my expect
what ever, thank you for your favor
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